| 数据搜索系统,热门电子元器件搜索 |
|
TLS115D0 数据表(PDF) 5 Page - Infineon Technologies AG |
|
|
|||||||||||||||||||||||||||||
TLS115D0 数据表(HTML) 5 Page - Infineon Technologies AG |
|
5 / 26 page ![]() TLS115D0 High Precision Voltage Tracker Pin configuration Data Sheet 5 Rev. 1.00 2016-10-13 2 Pin configuration 2.1 Pin assignment TLS115D0EJ in PG-DSO-8 EP package Figure 2 TLS115D0EJ pin Configuration 2.2 Pin definitions and functions TLS115D0EJ in PG-DSO-8 EP package Pin Symbol Function 1OUT Tracker output 150 mA output current capability Connect to GND with a capacitor close to the pins, respecting capacitance and ESR requirements given in Table 2 Functional range. 2N.C. Not connected 3GND Ground 4PG Power Good Open collector output. Connect via a pull-up resistor to a positive voltage rail. A “low” signal indicates a fault condition of the tracker output. 5ADJ Adjust Connect to the reference voltage 6N.C. Not Connected 7EN Enable input “High” signal: enables the tracker “Low” signal: disables the tracker If the enable function is not required, then connect EN to IN. 8IN Input It is recommended to connect a small ceramic capacitor to GND close to the pins in order to compensate line influence. Pad – Exposed Pad Connect to GND IN EN N.C. OUT N.C. GND PG ADJ 1 3 2 8 7 6 45 |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |