AD8338

Data Sheet

Rev. B | Page 12 of 19

THEORY OF OPERATION

INTRODUCTION

The AD8338 is a single-supply variable gain amplifier (VGA)

with an adjustable gain range of 80 dB. The AD8338 is an input

variable gain amplifier (IVGA) that accepts a wide range of

input amplitudes, and via its variable gain, compresses it to

either a narrow range of output amplitudes or a constant output

amplitude (for example, automatic gain control applications).

Like other VGAs from Analog Devices, Inc., the AD8338

possesses a constant bandwidth over the entire gain range.

Therefore, with a bandwidth of 18 MHz, the AD8338 achieves a

gain-bandwidth product of 180 GHz at its highest gain setting

(gain of 80 dB). Additionally, the differential output of the

AD8338 allows the VGA to directly drive differential input ADCs

without the need of a single-ended-to-differential converter.

OVERALL STRUCTURE OF THE AD8338

Figure 39 shows a block schematic of the AD8338 depicting the

key sections of the VGA and a general overview of its features.

The AD8338 signal path is comprised of the 500 Ω input

resistors, the VGA core, and the transimpedance output

amplifiers. The gain of the signal path is adjusted by the linear-

in-dB gain interface and the voltage at Pin GAIN with respect to

its local ground, Pin COMM. The automatic gain control (AGC)

circuit block is a current output rms detector that can be used

to drive the GAIN pin and configure the AD8338 as an AGC

amplifier with constant rms output amplitude. This output

amplitude is adjusted by the voltage at Pin VAGC with respect

to the voltage at Pin VREF. The offset null circuit block allows

the AD8338 to auto-zero any dc offset voltages. To enable the

offset null functionality, connect a capacitor between the OFSN

and VREF pins. To disable the offset null functionality, connect

Pin OFSN to ground. The INPD, INMD, FBKP, and FBKM pins

provide access to internal nodes in the VGA core of the AD8338

and output amplifiers, allowing the user to adjust the gain range,

output common-mode voltage, and bandwidth of the device.

INPR

INPD

INMD

INMR

MODE

COMM

GAIN

DETO

VAGC

VGA CORE

–26dB TO +54dB

OFFSET NULL

OFSN

VREF

VBAT

AUTOMATIC

GAIN

CONTROL

GAIN INTERFACE

AD8338

9.5kΩ

9.5kΩ

VREF

FBKP

OUTP

OUTM

FBKM

500Ω

500Ω

Figure 39. Block Schematic

VGA CORE

Figure 40 shows a simplified diagram of the VGA core at the heart

of the AD8338. The key concepts regarding the operation of

this VGA core are as follows. First, the ratio of the collector

currents in the two differential pairs (Q1, Q2 and Q3, Q4) is

identical given that the two differential pairs share the same base

drive. This ratio is represented by the modulation factor, x, where

values of x range from −1 to +1. Second, the input current

signal is forced into the collectors of the input differential pair

(Q1, Q2) by the loop amplifier to modulate the fixed tail

the input differential pair is replicated to the output differential

generate a differential output current. Third, the current gain of

current.

quadrant analog multiplier, exhibiting a linear relationship to

both the signal modulation factor, x, and this numerator current.

analog divider, having a hyperbolic gain function with respect

to the modulation factor, x, controlled by this denominator

adjust the gain of the amplifier. However, because a hyperbolic

gain function is generally of less value than one in which the

decibel gain is a linear function of a control input, the AD8338

includes a special interface to provide either increasing or

DENOMINATOR

BIAS CURRENT

Q1

Q2

Q4

Q3

2

+

–

LOOP

AMPLIFIER

2

NUMERATOR

BIAS CURRENT

2

2

Figure 40. Simplified Diagram of the VGA Core