ADRF6516ACPZ-R7 datasheet(17/29 Pages) AD

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Data Sheet

ADRF6516

Rev. C | Page 17 of 29

500

400

300

200

100

–100

100k

10M

100M

FREQUENCY (Hz)

BW = 2MHz

BW = 28MHz

14×

Figure 46. Sixth-Order Butterworth Group Delay Response for

0.5 dB Bandwidths Programmed to 2 MHz and 28 MHz

The corner frequency of the filters is defined by RC products,

which can vary by ±30% in a typical process. Therefore, all the

parts are factory calibrated for corner frequency, resulting in

a residual ±15% corner frequency variation over the −40°C to

+85°C temperature range. Although absolute accuracy requires

calibration, the matching of RC products between the pair of

channels is better than 1% by observing careful design and

layout practices. Calibration and excellent matching ensure

that the magnitude and group delay responses of both channels

track together, a critical requirement for digital IQ-based

communication systems.

VARIABLE GAIN AMPLIFIERS (VGAs)

The cascaded VGAs are based on the Analog Devices, Inc.,

patented X-AMP® architecture, consisting of tapped 25 dB

attenuators followed by programmable gain amplifiers. The

X-AMP architecture generates a continuous linear-in-dB

monotonic gain response with low ripple. The analog gains of

both cascaded VGA sections are controlled through the high

impedance GAIN pin with an accurate slope of 15 mV/dB.

The gain response shown in Figure 47 shows the GAIN pin

voltage range and the absence of gain foldback at high VGAIN.

By changing the gains of both VGAs simultaneously, a more

gradual variation in noise and distortion is achieved. The fixed

gain following each of the variable gain sections can also be pro-

grammed to two different values to maximize dynamic range.

–10

0.3

–0.3

VGAIN (V)

0.50

0.25

0.75 1.00

1.50

1.25

1.75 2.00 2.25 2.50 2.75 3.00

–0.2

–0.1

0.1

0.2

15mV/dB

Figure 47. Linear-in-dB Gain Control Response of the X-AMP VGA Cascade

Showing Consistent Slope and Low Error

OUTPUT BUFFERS/ADC DRIVERS

The low impedance (30 Ω) output buffers of the ADRF6516

are designed to drive either ADC inputs or subsequent amplifier

stages. They are capable of delivering up to 1.5 V p-p composite

two-tone signals into 1 kΩ differential loads with >65 dBc

IMD3. The output common-mode voltage defaults to VPS/2,

but it can be adjusted from 700 mV to 2.8 V without loss of

drive capability by presenting the VOCM pin with the desired

common-mode voltage. The high input impedance of VOCM

allows the ADC reference output to be connected directly. Even

though the output common-mode voltage is adjustable and the

offset compensation loop can null the accumulated dc offsets

(see the DC Offset Compensation Loop section), it may still be

desirable to ac couple the outputs by selecting the coupling cap-

acitors according to the load impedance and desired bandwidth.

DC OFFSET COMPENSATION LOOP

In many signal processing applications, no information is

carried in the dc level. In fact, dc voltages and other low

frequency disturbances can often dominate the intended signal

and consume precious dynamic range in the analog path and

bits in the data converters. These dc voltages can be present

with the desired input signal or can be generated inside the

signal path by inherent dc offsets or other unintended signal-

dependent processes such as self-mixing or rectification.

Because the ADRF6516 is fully dc-coupled, it may be necessary

to remove these offsets to realize the maximum signal-to-noise

ratio (SNR). This can be achieved with ac coupling capacitors at

the input and output pins; however, large value capacitors with

low impedance values are required because the high-pass corners

must be <10 Hz. To address the issue of dc offsets, the ADRF6516

provides an offset compensation loop that nulls the output differ-

ential dc level, as shown in Figure 48. If the compensation loop

is not required, it can be disabled by pulling the OFDS pin high.

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