M41ST95W datasheet(13/35 Pages) STMICROELECTRONICS

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M41ST95Y*, M41ST95W

READ and WRITE Cycles

Address and data are shifted MSB first into the Se-

rial Data Input (SDI) and out of the Serial Data

Output (SDO). Any data transfer considers the first

bit to define whether a READ or WRITE will occur.

This is followed by seven bits defining the address

to be read or written. Data is transferred out of the

SDO for a READ operation and into the SDI for a

WRITE operation. The address is always the sec-

ond through the eighth bit written after the Enable

(E) pin goes low. If the first bit is a '1,' one or more

WRITE cycles will occur. If the first bit is a '0,' one

or more READ cycles will occur (see Figure 12

and Figure 13., page 14).

Data transfers can occur one byte at a time or in

multiple byte burst mode, during which the ad-

dress pointer will be automatically incremented.

For a single byte transfer, one byte is read or writ-

ten and then E is driven high. For a multiple byte

transfer all that is required is that E continue to re-

main low. Under this condition, the address pointer

will continue to increment as stated previously. In-

crementing will continue until the device is dese-

lected by taking E high. The address will wrap to

00h after incrementing to 3Fh.

The system-to-user transfer of clock data will be

halted whenever the address being read is a clock

address (00h to 07h). Although the clock contin-

ues to maintain the correct time, this will prevent

updates of time and date during either a READ or

WRITE of these address locations by the user.

The update will resume either due to a deselect

condition or when the pointer increments to an

non-clock or RAM address (08h to 3Fh).

Note: This is true both in READ and WRITE mode.

Figure 12. READ Mode Sequence

SCL

SDI

SDO

HIGH IMPEDANCE

W/R BIT

7 BIT ADDRESS

MSB

DATA OUT

MSB

(BYTE 1)

DATA OUT

(BYTE 2)

12 13 14 15 16 17

AI04635

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