M41ST95W datasheet(17/35 Pages) STMICROELECTRONICS

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M41ST95Y*, M41ST95W

Calibrating the Clock

The M41ST95Y/W is driven by a quartz-controlled

oscillator with a nominal frequency of 32,768Hz.

Uncalibrated clock accuracy will not exceed ±35

ppm (parts per million) oscillator frequency error at

25°C, which equates to about ±1.53 minutes per

month. When the Calibration circuit is properly em-

ployed, accuracy improves to better than ±2 ppm

at 25°C.

The oscillation rate of crystals changes with tem-

perature (see Figure 18., page 24). Therefore, the

M41ST95Y/W design employs periodic counter

correction. The calibration circuit adds or subtracts

counts from the oscillator divider circuit at the di-

vide

256

stage,

shown

Figure

19., page 24. The number of times pulses are

blanked (subtracted, negative calibration) or split

(added, positive calibration) depends upon the

value loaded into the five Calibration Bits found in

the Control Register. Adding counts speeds the

clock up, subtracting counts slows the clock down.

The Calibration Bits occupy the five lower order

bits (D4-D0) in the Control Register (8h). These

bits can be set to represent any value between 0

and 31 in binary form. Bit D5 is a Sign Bit; '1' indi-

cates positive calibration, '0' indicates negative

calibration. Calibration occurs within a 64 minute

cycle. The first 62 minutes in the cycle may, once

per minute, have one second either shortened by

128 or lengthened by 256 oscillator cycles. If a bi-

nary '1' is loaded into the register, only the first 2

minutes in the 64 minute cycle will be modified; if

a binary 6 is loaded, the first 12 will be affected,

and so on.

Therefore, each calibration step has the effect of

adding 512 or subtracting 256 oscillator cycles for

every 125,829,120 actual oscillator cycles, that is

+4.068 or –2.034 ppm of adjustment per calibra-

tion step in the calibration register. Assuming that

the oscillator is running at exactly 32,768Hz, each

of the 31 increments in the Calibration byte would

represent +10.7 or –5.35 seconds per month

which corresponds to a total range of +5.5 or –2.75

minutes per month.

Two methods are available for ascertaining how

much calibration a given M41ST95Y/W may re-

quire.

The first involves setting the clock, letting it run for

a month and comparing it to a known accurate ref-

erence and recording deviation over a fixed period

of time. Calibration values, including the number of

seconds lost or gained in a given period, can be

found in Application Note AN934: TIMEKEEPER

CALIBRATION. This allows the designer to give

the end user the ability to calibrate the clock as the

environment requires, even if the final product is

packaged in a non-user serviceable enclosure.

The designer could provide a simple utility that ac-

cesses the Calibration Byte.

The second approach is better suited to a manu-

facturing environment, and involves the use of the

IRQ/FT/OUT pin. The pin will toggle at 512Hz,

when the Stop Bit (ST, D7 of 1h) is '0,' the Fre-

quency Test Bit (FT, D6 of 8h) is '1,' the Alarm Flag

Enable Bit (AFE, D7 of Ah) is '0,' and the Watch-

dog Steering Bit (WDS, D7 of 9h) is '1' or the

Watchdog Register (9h = 0) is reset.

Any deviation from 512Hz indicates the degree

and direction of oscillator frequency shift at the test

temperature.

For

example,

reading

512.010124Hz would indicate a +20 ppm oscillator

frequency error, requiring a –10 (XX001010) to be

loaded into the Calibration Byte for correction.

Note: Setting or changing the Calibration Byte

does not affect the Frequency Test output fre-

quency.

The IRQ/FT/OUT pin is an open drain output

which requires a pull-up resistor for proper opera-

tion. A 500 to 10k

Ω resistor is recommended in or-

der to control the rise time. The FT Bit is cleared

on power-down.

Setting Alarm Clock Registers

Address locations 0Ah-0Eh contain the alarm set-

tings. The alarm can be configured to go off at a

prescribed time on a specific month, date, hour,

minute, or second, or repeat every year, month,

day, hour, minute, or second. It can also be pro-

grammed to go off while the M41ST95Y/W is in the

battery back-up to serve as a system wake-up call.

Bits RPT5-RPT1 put the alarm in the repeat mode

of operation. Table 5., page 18 shows the possible

configurations. Codes not listed in the table default

to the once per second mode to quickly alert the

user of an incorrect alarm setting.

When the clock information matches the alarm

clock settings based on the match criteria defined

by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE

(Alarm Flag Enable) is also set, the alarm condi-

tion activates the IRQ/FT/OUT pin.

Note: If the address pointer is allowed to incre-

ment to the Flag Register address, an alarm con-

dition will not cause the Interrupt/Flag to occur until

the address pointer is moved to a different ad-

dress.

It should also be noted that if the last address writ-

ten is the “Alarm Seconds,” the address pointer

will increment to the Flag address, causing this sit-

uation to occur.

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