TAS5805MPWPR datasheet(21/86 Pages) TI1

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Serial Audio

Interface (Input)

DSP

(Including

interpolator)

Delta Sigma

Modulator

DAC

Audio In

LRCLK/FS

DSPCLK

OSRCLK

DACCLK

TAS5805M

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SLASEH5A – MAY 2018 – REVISED JULY 2018

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9.3 Feature Description

9.3.1 Power Supplies

To facilitate system design, TAS5805M needs only a 3.3-V or 1.8-V supply in addition to the (typical) 12-V or 24-

V power-stage supply. Two internal voltage regulators provide suitable voltage levels for the gate drive circuitry

and internal circuitry. The external pins are provided only as a connection point for off-chip bypass capacitors to

filter the supply. Connecting external circuitry to these regulator outputs may result in reduced performance and

damage to the device. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive,

is accommodated by built-in bootstrap circuitry requiring only a few external capacitors. In order to provide good

electrical and acoustical characteristics, the PWM signal path for the output stage is designed as identical,

independent half-bridges. For this reason, each half-bridge has separate bootstrap pins (BST_x). The gate drive

voltages (AVDD) are derived from the PVDD voltage. Special attention should be paid to placing all decoupling

capacitors as close to their associated pins as possible. In general, inductance between the power-supply pins

and decoupling capacitors must be avoided. For a properly functioning bootstrap circuit, a small ceramic

capacitor must be connected from each bootstrap pin (BST_x) to the power-stage output pin (OUT_x). When the

power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the

gate-drive regulator output pin (AVDD) and the bootstrap pin. When the power-stage output is high, the bootstrap

capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-

side gate driver.

9.3.2 Device Clocking

The TAS5805M devices have flexible systems for clocking. Internally, the device requires a number of clocks,

mostly at related clock rates to function correctly. All of these clocks can be derived from the Serial Audio

Interface.

Figure 55. Audio Flow with Respective Clocks

Figure 55 shows the basic data flow and clock distribution.

The Serial Audio Interface typically has 3 connection pins which are listed as follows:

•

SCLK (Bit Clock)

•

LRCLK/FS (Left Right Word Clock and Frame Sync)

•

SDIN (Input Data)

The device has an internal PLL that is used to take SCLK and create the higher rate clocks required by the DSP

and the DAC clock.

The TAS5805M device has an audio sampling rate detection circuit that automatically senses the sampling

frequency. Common audio sampling frequencies of 32 kHz, 44.1kHz – 48 kHz, 88.2 kHz – 96 kHz with ±5%

tolerance are supported. The sampling frequency detector sets the clock for DAC and DSP automatically.

9.3.3 Serial Audio Port – Clock Rates

The serial audio interface port is a 3-wire serial port with the signals LRCLK/FS, SCLK, and SDIN. SCLK is the

serial audio bit clock, used to clock the serial data present on SDIN into the serial shift register of the audio

interface. Serial data is clocked into the TAS5805M device on the rising edge of SCLK. The LRCK/FS pin is the

serial audio left/right word clock or frame sync when the device is operated in TDM Mode.

TAS5805MPWPR 数据表(PDF) 21 Page - Texas Instruments

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