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TAS5805MPWPR 数据表(PDF) 22 Page - Texas Instruments |
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TAS5805MPWPR 数据表(HTML) 22 Page - Texas Instruments |
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22 / 86 page ![]() LRCLK/FS SCLK Audio data word = 16-bit, SCLK = 32, 64fs DATA 1 2 15 16 MSB LSB 1 2 15 16 MSB LSB Audio data word = 24-bit, SCLK = 64fs DATA 1 2 23 24 MSB LSB 1 2 23 24 MSB LSB Audio data word = 32-bit, SCLK = 64fs DATA 1 2 31 32 MSB LSB 1 2 31 32 MSB LSB 1 tS Left-channel Right-channel 22 TAS5805M SLASEH5A – MAY 2018 – REVISED JULY 2018 www.ti.com Product Folder Links: TAS5805M Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated Feature Description (continued) Table 1. Audio Data Formats, Bit Depths and Clock Rates FORMAT DATA BITS MAXIMUM LRCLK/FS FREQUENCY (kHz) SCLK RATE (fS) I2S/LJ/RJ 32, 24, 20, 16 Up to 96 64, 32 TDM 32, 24, 20, 16 Up to 48 128,256,512 96 128,256 When any kind of clock errors including Out of Range, SCLK-FSYNC Ratio, or Clock halt are detected, the device puts all channels into the Hi-Z state and reports Clock Error in Register 113 (Register Address 0x71). When all audio clocks are within the expected ranges, the device automatically returns to the state it was in. 9.3.4 Serial Audio Port - Data Formats and Bit Depths The device supports industry-standard audio data formats, including standard I2S, left-justified, right-justified and TDM/DSP data. Data formats are selected via Register (P0-R51-D[5:4]). If the high width of LRCK/FS in TDM/DSP mode is less than 8 cycles of SCK, the register (P0-R51-D[3:2]) should be set to 01. All formats require binary two's complement, MSB-first audio data; up to 32-bit audio data is accepted. All the data formats, word length and clock rate supported by this device are shown in Table 1. The data formats are detailed in Figure 56 through Figure 60. The word length are selected via Register (P0-R51-D[1:0]). The offsets of data are selected via Register (P0-R51-D[7]) and Register (P0-R52-D[7:0]). Default setting is I2S and 24 bit word length. Figure 56. Left-Justified Audio Data Format |
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