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ADAU7002ACBZ-R7 数据表(PDF) 10 Page - Analog Devices

部件名 ADAU7002ACBZ-R7
功能描述  Stereo PDM-to-I2S or TDM Conversion IC
PDF  16 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADAU7002ACBZ-R7 数据表(HTML) 10 Page - Analog Devices

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ADAU7002
Data Sheet
Rev. B | Page 10 of 16
Serial Port Timing
Figure 13. Serial Port Timing Diagram
IOVDD = 1.62 V to 3.63 V, load capacitance = 25 pF, unless otherwise noted.
Table 7. I2S/TDM Timing Parameters
Parameter
Symbol
tMIN
tMAX
Unit
BCLK Pulse Width High
tBIH
10
ns
BCLK Pulse Width Low
tBIL
10
ns
LRCLK Setup Time
tLIS
10
ns
LRCLK Hold Time
tLIH
10
ns
Time from BCLK Falling
tSODM
18
ns
Figure 14. I2S, CONFIG Pin Tied to IOVDD
Figure 15. TDM8 Channel 1 and Channel 2, CONFIG Pin Tied to GND
BCLK
LRCLK
SDATA
TDM MODE
SDATA
I2S JUSTIFIED
MODE
tBIH
MSB
MSB
MSB – 1
tBIL
tLIS
tLIH
tSODM
tSODM
LRCLK
BCLK
SDATA
I2S LEFT CHANNEL
20
BCLKs
I2S RIGHT CHANNEL
TRISTATE
TRISTATE
SLOT 1
LRCLK
BCLK
SDATA
20
BCLKs
RIGHT
LEFT
SLOT 2
SLOT 3
SLOT 4
SLOT 5
SLOT 6
SLOT 7
SLOT 8
TRISTATE
TRISTATE
TRISTATE
TRISTATE
TRISTATE
TRISTATE



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