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SSM6322ACPZ-R7 数据表(PDF) 6 Page - Analog Devices

部件名 SSM6322ACPZ-R7
功能描述  High Fidelity, Low Power, Integrated Stereo Audio Amplifier
PDF  20 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

SSM6322ACPZ-R7 数据表(HTML) 6 Page - Analog Devices

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SSM6322
Data Sheet
Rev. 0 | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Rating
Supply Voltage
Single Supply
12.6 V
Dual Supply
±6.3 V
Exposed Pad Voltage
−VSY or ground
Storage Temperature Range
−65°C to +125°C
Operating Temperature Range
−40°C to + 85°C
Lead Temperature (Soldering 10 sec)
300°C
Junction Temperature
150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to PCB design and
operating environment. Careful attention to PCB thermal
design is required. The values in Table 4 were obtained per
JEDEC standard JESD51-12.
Table 4. Thermal Resistance
Package Type
θJA
θJC
Unit
CP-24-15
47
3.3
°C/W
Board layout impacts thermal characteristics, such as θJA. When
proper thermal management techniques are used, a better θJA
value can be achieved.
Although the exposed pad can be left floating, it must be connected
to an external V− plane or ground plane for proper thermal
management.
Maximum Power Dissipation
The maximum safe power dissipation for the SSM6322 is limited
by the associated rise in junction temperature (TJ) on the die. At
approximately 150C, which is the glass transition temperature,
the properties of the plastic change. Even temporarily exceeding
this temperature limit may change the stresses that the package
exerts on the die, permanently shifting the parametric performance
of the SSM6322. Exceeding a junction temperature of 175C
for an extended period can result in changes in silicon devices,
potentially causing degradation or loss of functionality. The power
dissipated in the package (PD) is the sum of the quiescent power
dissipation and the power dissipated in the die due to the
SSM6322 drive at the output.
The quiescent power is the voltage between the supply pins (VS)
times the quiescent current (IS).
PD = Quiescent Power + (Total Drive Power − Load Power)

L
2
OUT
L
OUT
S
S
S
D
R
V
R
V
2
V
I
V
P


Consider the rms output voltages. If RL is referenced to −VSY, as
in single-supply operation, the total drive power is VSY × IOUT. If
the rms signal levels are indeterminate, consider the worst case,
when VOUT = VSY/4 for RL to midsupply.
 
L
S
S
S
D
R
/
V
I
V
P
2
4
Airflow increases heat dissipation, effectively reducing θJA.
Also, more metal directly in contact with the package leads and
exposed paddle from metal traces, through holes, ground, and
power planes reduce θJA.
Figure 2 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 24-lead LFCSP
package on a JEDEC standard 4-layer board.
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
–40
–25
–10
5
20
35
50
65
80
AMBIENT TEMPERATURE (°C)
Figure 2. Maximum Power Dissipation vs. Ambient Temperature for a
4-Layer Board
ESD CAUTION



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