Data Sheet

SSM6322

Rev. 0 | Page 17 of 20

Assuming there is no common-mode control (see Figure 40),

the signals at the input terminals (VP2/VN2) are ac signals that

have the same amplitude and phase. In addition, the internal

voltage source of the DAC is differential, which makes the

degrades the performance of the DAC. Simultaneously, from the

amplifier, the ac common-mode signal at two input terminals (VP2

and VN2) generates additional error signal at the output by its

limited ac common-mode rejection ratio (CMRR) performance.

After a common-mode control circuit (indicated by the dashed

outline shown in Figure 42) is included, the signal at the input

terminals (VP2 and VN2) is a dc signal set by the voltage at the

REF2 pin (typically this voltage is the same as the dc common-

the DAC is the same. Additionally, the high dc CMRR performance

of the amplifier renders the CMRR error negligible. Both the

DAC and the amplifier have the best performance in this

configuration. The SSM6322 implements the circuit shown

in Figure 42.

SSM6322

INPUT

REF2

AUDIO

DAC

GND2

VEE2 VCC2

GAIN2

VP2

VN2

9

4

5

6

11

12

7

Figure 42. Common-Mode Circuit with Common-Mode Control

CAPACITIVE LOAD DRIVE

Figure 43 shows the schematic of the output stage for driving

capacitive loads. Figure 44 and Figure 45 show the frequency

response for a gain of 1 at the ±5 V and ±3.3 V power supply

voltages, respectively. The peaking is high with a small

frequency response is flat and without peaking.

499Ω

10Ω

600Ω

Figure 43. Schematic for Driving Capacitive Loads

20

10

0

–10

–20

–30

–40

–50

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

CL2 = 330pF

CL2 = 470pF

CL2 = 1nF

CL2 = 2.2nF

20

10

0

–10

–20

–30

–40

–50

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

CL2 = 330pF

CL2 = 470pF

CL2 = 1nF

CL2 = 2.2nF