Rev. 3.5

RI-RFM-006A

Page 7 of 19

3.

Receiving Mode

In the Receiving Mode, the frequency-shift-keyed data signals are sequentially digitized to discriminate

their frequencies by binary notation (high-low) and demodulate them into bit strings consisting of bit data

“1” and “0”.

For binary discrimination of signal frequencies between high and low, the frequency level of each

FS-keyed signal is measured from its leading edge at the “A3OP” terminal through to the next leading

edge by count of the internal master clock, as shown below. The threshold for this counted value

(x in the diagram below) is fixed at 132; when the clock count is over 132, it results in a negative level

output at the “RXDT-“ terminal (bit data ”1”), and when the clock count does not reach 132, a positive

level output at the same terminal (bit data “0”), respectively.

As the normal frequency of the internal master clock is 17.1776 MHz, one clock count is equivalent to

130.133... kHz (17.1776 MHz divided by 132 = 130.133... kHz). Accordingly, a signal is identified as bit

data “1” with the resulting negative level output at the “RXDT-“ terminal when the signal frequency at

the “A3OP” terminal is 130.133... kHz or less, and it is identified as bit data “0” with the resulting

positive level output at the “RXDT-“ terminal when the signal frequency at the “A3OP” terminal is over

130.133... kHz.

An additional feature is included to maximize the stability of the above-mentioned FSK signal

demodulating system based on binary notation: the system incorporates a circuit which disables definition

of an “RXDT-“ signal unless more than four consecutive FS-keyed signal waves are identified within the

same frequency band during binary discrimination. This protects the once defined “RXDT-“ signal in the

bit data form from being affected by sporadic events. For instance, even when its discrimination result is

sporadically inverted due to some noise effects, it is not affected if only three or less consecutive FS-

keyed signal waves are identified at the “A3OP” terminal. (See the diagram below.)

Note: For the timing between “A3OP” and “RXDT-“ signals, refer to the section describing

“Input-Output Specifications”.

The signals demodulated through the above-mentioned process are sequentially output from the “RXDT-“

Internal master clock

Signals discriminated

at A3OP terminal

Clock counts

1

1

234

56

X

X-1

23

4567

Internal frequency

discriminating signals

Signal

discriminated

at A3OP terminal

RXDT- terminal

output signals

DATA VALID

DATA VALID