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TSS901EASC 数据表(PDF) 10 Page - ATMEL Corporation |
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TSS901EASC 数据表(HTML) 10 Page - ATMEL Corporation |
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10 / 31 page  10 TSS901E Rev. C – 24-Aug-01 TSS901E channel 3 status and control registers 36 36 36 CH2_PR_STAR channel 2 Protocol Status Register 04 r / w 37 37 37 reserved 00 38 38 38 CH2_CNTRL1 channel 2 control Register 1 00 r / w 39 39 39 CH2_CNTRL2 channel 2 control Register 2 00 r / w 3A 3A 3A CH2_HTID channel 2 Header Transaction ID byte 00 ro 3B 3B 3B CH2_HCNTRL channel 2 Header control byte 00 ro 3C 3C 3C CH2_ESR1 channel 2 detailed error source register 1 00 r / w 3D 3D 3D CH2_ESR2 channel 2 detailed error source register 2 00 r / w 3E 3E 3E reserved 00 3F 3F 3F CH2_COMICFG channel 2 COMI configuration register 00 r / w 40 40 40 41 CH2_TX_SAR channel 2 transmit Start Address Register 00 r / w 42 42 42 43 CH2_TX_EAR channel 2 transmit End Address Register 00 r / w 44 44 44 45 CH2_TX_CAR channel 2 transmit Current Address Register 00 ro 46 46 46 CH2_TX_FIFO channel 2 transmit FIFO 00 wo 47 47 47 CH2_TX_EOPB channel 2 transmit EOP Bit Register 00 wo 48 48 48 49 CH2_RX_SAR channel 2 receive Start Address Register 00 r / w 4A 4A 4A 4B CH2_RX_EAR channel 2 receive End Address Register 00 r / w 4C 4C 4C 4D CH2_RX_CAR channel 2 receive Current Address Register 00 ro 4E 4E 4E CH2_RX_FIFO channel 2 receive FIFO xxxxxxxx ro 4F 4F 4F CH2_STAR channel 2 Status Register 01 ro Port Width / Address (hex) Register Function Reset Value (hex) Access 32 16 8 Port Width / Address (hex) Register Function Reset Value (hex) Access 32 16 8 50 50 50 CH3_DSM_MODR channel 3 DSM mode Register 03 r / w 51 51 51 CH3_DSM_CMDR channel 3 DSM command Register 00 r / w 52 52 52 CH3_DSM_STAR channel 3 DSM status Register 00 r / w |
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