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TSS901E

Rev. C – 24-Aug-01

Fault Tolerance

The IEEE Std 1355-1995 specifies low level checks as link disconnect detection and

parity check at token level. The TSS901E provides, through the Protocol Processing

Unit, features to reset a link or all links inside the TSS901E, to reset the local CPU or to

send special signals to the CPU commanded via the links.

Additionally it is possible to enable a checksum coder/decoder to have fault detection

capabilities at packet level.

Applications

The TSS901E is a very high speed, scalable link-interface chip with fault tolerance fea-

tures. The initial exploitation is for use in multi-processor systems where the

standardisation or the high speed of the links is an important issue and where reliability

is a requirement. Further application examples are heterogeneous systems or modules

without any communication features as special image compression chips, certain signal

processors (TSC21020F, ERC32, ...), application specific programmable logic or mass

memory.

The TSS901E could also be used for single board systems where standardised high

speed interfaces are needed. Even "non-intelligent" modules such as A/D-converter or

sensor interfaces can be assembled with the TSS901E because of the "control by link"

feature. The complete control of the TSS901E can be done via link from a central con-

troller-node.