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ADCLK905BCPZ-R2 数据表(PDF) 9 Page - Analog Devices

部件名 ADCLK905BCPZ-R2
功能描述  Ultrafast SiGe ECL Clock/Data Buffers
PDF  16 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADCLK905BCPZ-R2 数据表(HTML) 9 Page - Analog Devices

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Data Sheet
ADCLK905/ADCLK907/ADCLK925
Rev. B | Page 9 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = 3.3 V, VEE = 0.0 V, TA = 25°C, outputs terminated 50 Ω to VCC − 2 V, unless otherwise noted.
Q
Q
1.37V
200ps/DIV
2.37V
Figure 7. Output Waveform, VCC = 3.3 V
–90
–100
–110
–120
–130
–140
–150
–160
–170
10
100
1k
10k
100k
1M
10M
100M
f (Hz)
AGILENT E5500
CARRIER: 122.88MHz
NO SPURS
Figure 8. Phase Noise at 122.88 MHz
–90
–100
–110
–120
–130
–140
–150
–160
–170
10
100
1k
10k
100k
1M
10M
100M
f (Hz)
AGILENT E5500
CARRIER: 245.76MHz
NO SPURS
Figure 9. Phase Noise at 245.76 MHz
Q
Q
100ps/DIV
1.37V
2.37V
Figure 10. Output Waveform, VCC = 3.3 V
–90
–100
–110
–120
–130
–140
–150
–160
–170
10
100
1k
10k
100k
1M
10M
100M
f (Hz)
AGILENT E5500
CARRIER: 622.08MHz
NO SPURS
Figure 11. Phase Noise at 622.08 MHz
0
50
100
150
200
250
300
0
1
2
3
4
5
6
7
8
INPUT SLEW RATE (V/ns)
Figure 12. RMS Jitter vs. Input Slew Rate



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