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ADCLK905BCPZ-R2 数据表(PDF) 13 Page - Analog Devices

部件名 ADCLK905BCPZ-R2
功能描述  Ultrafast SiGe ECL Clock/Data Buffers
PDF  16 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADCLK905BCPZ-R2 数据表(HTML) 13 Page - Analog Devices

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Data Sheet
ADCLK905/ADCLK907/ADCLK925
Rev. B | Page 13 of 16
TYPICAL APPLICATION CIRCUITS
VREF
VCC
VT
D
D
CONNECT VT TO VCC.
Figure 26. Interfacing to CML Inputs
VREF
VCC – 2V
VT
D
D
CONNECT VT TO VCC − 2V.
Figure 27. Interfacing to PECL
VREF
VT
D
D
NOTES
1. PLACING A BYPASS CAPACITOR
FROM VT TO GROUND CAN IMPROVE
THE NOISE PERFORMANCE.
CONNECT VT TO VREF.
Figure 28. AC Coupling Differential Signals
VREF
VT
D
D
CONNECT VT, VREF, AND D. PLACE A BYPASS
CAPACITOR FROM VT TO GROUND.
ALTERNATIVELY, VT, VREF, AND D CAN BE
CONNECTED, GIVING A CLEANER LAYOUT AND
A 180º PHASE SHIFT.
Figure 29. Interfacing to AC-Coupled Single-Ended Inputs



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