CM6503/4

2002/07/16

Champion Microelectronic Corporation

Page 6

Functional Description

The CM6503/4 consists of an ICST (Input Current Shaping

Technique), CCM (Continuous Conduction Mode) or DCM

(Discontinuous Conduction Mode) boost PFC (Power

Factor Correction) front end and a synchronized PWM

Clock to synchronize the down stream DC to DC PWM

stage.. The CM6503/4 is pin to pin compatible with

FAN6503/4. It is distinguished from earlier combo

controllers by its low count, innovative input current shaping

technique, and very low start-up and operating currents.

PWM clock is to synchronize the conventional trailing-edge

modulation DC to DC PWM stage, while the PFC uses

leading-edge modulation. This patented Leading

Edge/Trailing Edge (LETE) modulation technique helps to

minimize ripple current in the PFC DC buss capacitor.

Key features of CM6503/4:

1.) Voltage Error Amplifier is the slew rate

enhancement transconductance amplifier, gmv.

This transconductance amplifier will increase the

transient response 5 to 10 times from the

conventional OP

2.) VFB PFC OVP comparator

3.) Tri-fault Detect for UL1950 compliance and

enhanced safety

4.) A feedforward signal from IAC pin is added to do

the automatic slope compensation. This

increases the signal to noise ratio during the light

load; therefore, THD is improved at light load and

high input line voltage.

5.) CM6503 does not require the bleed resistor and

it uses the less than 500k ohm resistor between

IAC pin and rectified line voltage to feed the

initial current before the chip wakes up.

6.) VINOK comparator is added to guaranteed PWM

Clock cannot turn on until VFB reaches 2.5V in which

PFC boost output is about steady state, typical 380V.

7.) 8 pin packages

8.) No internal Zener which has been replaced with

VCCOVP comparator

The CM6503 operates both PFC and PWM sections at

67kHz, while the CM6504 operates the PWM section at

twice the frequency (134kHz) of the PFC. This allows the

use of smaller PWM magnetic and output filter components,

while minimizing switching losses in the PFC stage.

Several protection features have been built into the

CM6503/4. These include soft-start, redundant PFC

overvoltage protection, Tri-Fault Detect, VINOK, peak

current limiting, duty cycle limiting, under-voltage lockout,

reference ok comparator and VCCOVP.

Detailed Pin Descriptions

PFC OUT (Pin 1)

PFC OUT is the high-current power driver capable of

directly driving the gate of a power MOSFET with peak

currents up to -1A and +0.5A. Both outputs are actively held

low when VCC is below the UVLO threshold level which is

15V or VREFOK comparator is low.

GND (Pin 2)

GND is the return point for all circuits associated with this

part. Note: a high-quality, low impedance ground is critical to

the proper operation of the IC. High frequency grounding

techniques should be used.

ISENSE (Pin 3)

This pin ties to a resistor which senses the PFC input

current. This signal should be negative with respect to the IC

ground. It internally feeds the pulse-by-pulse current limit

comparator and the current sense feedback signal. The

ILIMIT trip level is –1V. The ISENSE feedback is internally

multiplied by a gain of four and compared against the internal

programmed ramp to set the PFC duty cycle. The

intersection of the boost inductor current downslope with the

internal programming ramp determines the boost off-time.

It requires a RC filter between ISENSE and PFC boost

sensing resistor.

VEAO (Pin 4)

This is the PFC slew rate enhanced transconductance

amplifier output which needs to connected with a

compensation network.

VFB (Pin 5)

Besides this is the PFC slew rate enhanced

transconductance input, it also tie to a couple of protection

comparators, PFCOVP, and Tri-Fault Detect.

IAC (pin 6)

Typically, it has a feedforward resistor, RAC, less than 500K

ohm resistor connected between this pin and rectified line

input voltage.

This pin serves 2 purposes:

1.) During the startup condition, it supplies the startup

current; therefore, the system does not requires

additional bleed resistor to start up the chip.

2.) The current of RAC will program the automatic

slope compensation for the system. This

feedforward signal can increase the signal to noise

ratio for the light load condition or the high input line

voltage condition.

VCC (Pin 7)

VCC is the power input connection to the IC. The VCC

start-up current is 100uA. The no-load ICC current is 2mA.

VCC quiescent current will include both the IC biasing

currents and the PFC output currents. Given the operating

frequency and the MOSFET gate charge (Qg), average PFC

output currents can be calculated as IOUT = Qg x F. The

average magnetizing current required for any gate drive

transformers must also be included. The VCC pin is also

assumed to be proportional to the PFC output voltage.

Internally it is tied to the VCC OVP comparator (19.4V)

providing redundant high-speed over-voltage protection

(OVP) of the PFC stage. VCC also ties internally to the

UVLO circuitry and VREFOK comparator, enabling the IC at

15V and disabling it at 10V. VCC must be bypassed with a

high quality ceramic bypass capacitor placed as close as