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CM6503IP 数据表(PDF) 11 Page - List of Unclassifed Manufacturers

部件名 CM6503IP
功能描述  8-PIN SINGLE PFC CONTROLLER WITH 50% PWM CLOCK SIGNAL
PDF  13 Pages
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制造商  ETC [List of Unclassifed Manufacturers]
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标志 ETC - List of Unclassifed Manufacturers

CM6503IP 数据表(HTML) 11 Page - List of Unclassifed Manufacturers

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CM6503/4
8-PIN SINGLE PFC CONTROLLER WITH 50% PWM CLOCK SIGNAL
2002/07/16
Preliminary Rev. 0.2
Champion Microelectronic Corporation
Page 11
50% PWM Clock
PWMCLK is the PWM Clock signal for the down stream DC
to DC PWM stage. This signal will not be on until the PFC
boost output reaches steady state which means VFB has
reaches 2.45V. (Typical PFC boost output is around 380V.
Then PWMCLK will send out 50% clock signal which has
been perfectly aligned with PFCOUT signal which is leading
edge modulation.
In CM6503, 50% PWM Clock is running at 67.5K hz. In
CM6504, 50% PWM Clock is running at 135Khz.
APPLICATION CIRCUIT (CM6503/4)
D8
R7
F1
AC IN
19.4V
R1A
UVLO
0.75V
10mS
..
.
D2
C15
400K ohm
C8
To synchronize
next DC to DC
stage
R1B
VREF OK
R5
D3
S
R
Q
Q
R
PFCCLKB
PWMCLK
OSC
.
.
67KHz
VFB
2
GND
Q1
134KHz
R2
CFilter
67KHz
R1C
C7
18V
C14
VCC OVP
+
-
.
-
C1
SS
VREFOK
PFC ILIMIT
+
-
.
8
PWMCLK
C8
..
+
+
OUT
U1
SUM
.
.
.
50%
UVLO
..
+
-
.
T1
RAMP
+
-
.
PFC OVP
+
-
.
-
7
VCC
PFCCMP
+
-
.
-1V
Tri-Fault
Detect
4
VEAO
C5
D1
R3
67KHz
CM6504
1K ohm
3
ISENSE
1V
D4
pwm clk=
Z1
100K ohm
1
PFCOUT
D5
2.5V
CM6503
C4
VIN OK
+
-
.
+
6
IAC
D7
fpfc=
RFIlter
T1
2.5V
C9
FAULTB
gmv
2.5V
R11
D11
0.5V
pwm clk=
VREF OK
ISENSEAMP
VCC
SS
PWM CLK
5
VFB
R4
2.75V
fpfc=
C13
VCC
RAC
PFCCLKB



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