CM6503IP datasheet(9/13 Pages) ETC

9 / 13 page

CM6503/4

8-PIN SINGLE PFC CONTROLLER WITH 50% PWM CLOCK SIGNAL

2002/07/16

Preliminary Rev. 0.2

Champion Microelectronic Corporation

Page 9

One of the advantages of this control technique is that it

required only one system clock. Switch 1(SW1) turns OFF

and switch 2 (SW2) turns ON at the same instant to

minimize the momentary “no-load” period, thus lowering

ripple voltage generated by the switching action. With such

synchronized switching, the ripple voltage of the first stage

is reduced. Calculation and evaluation have shown that the

120Hz component of the PFC’s output ripple voltage can be

reduced by as much as 30% using this method,

substantially reducing dissipation in the high-voltage PFC

capacitor.

Typical Applications

PFC Section:

PFC Voltage Loop Error Amp, VEAO

The ML4803 utilizes an one pin voltage error amplifier in

the PFC section (VEAO). In the CM6503/4, it is using the

slew rate enhanced transconductance amplifier, which is

the same as error amplifier in the CM6800. The unique

transconductance profile can speed up the conventional

transient response by 10 times. The internal reference of

the VEAO is 2.5V. The input of the VEAO is VFB pin.

PFC Voltage Loop Compensation

The voltage-loop bandwidth must be set to less than 120Hz

to limit the amount of line current harmonic distortion. A

typical crossover frequency is 30Hz.

The Voltage Loop Gain (S)

EAO

OUTDC

EAO

OUT

EAO

OUT

∆

≈

∆

ZCV: Compensation Net Work for the Voltage Loop

GMv: Transconductance of VEAO

PIN: Average PFC Input Power

VOUTDC: PFC Boost Output Voltage; typical designed value is

380V.

CDC: PFC Boost Output Capacitor

∆VEAO: This is the necessary change of the VEAO to deliver

the designed average input power. The average value is

6V-3V=3V since when the input line voltage increases, the

delta VEAO will be reduced to deliver the same to the output.

To over compensate, we choose the delta VEAO is 3V.

Internal Voltage Ramp

The internal ramp current source is programmed by way of

VEAO pin voltage. When VEAO increases the ramp current

source is also increase. This current source is used to

develop the internal ramp by charging the internal 30pF +12/

-10% capacitor. The frequency of the internal programming

ramp is set internally to 67kHz.

Design PFC ISENSE Filtering

ISENSE Filter, the RC filter between Rs and ISENSE:

There are 2 purposes to add a filter at ISENSE pin:

1.) Protection: During start up or inrush current

conditions, it will have a large voltage cross Rs,

which is the sensing resistor of the PFC boost

converter. It requires the ISENSE Filter to attenuate

the energy.

2.) Reduce L, the Boost Inductor: The ISENSE Filter

also can reduce the Boost Inductor value since the

ISENSE Filter behaves like an integrator before

going ISENSE which is the input of the current error

amplifier, IEAO.

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