S72XS-R datasheet(3/7 Pages) CYPRESS

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S72XS-R MCP

Document Number: 002-00772 Rev. *J

Page 3 of 7

Signal Description

Table 4. Input/Output Description

Symbol

Description

Flash RAM

ADQ15 – ADQ0

Flash multiplexed Address and Data



F-CE#

Flash Chip-enable input



F-OE#

Flash Output Enable input. Asynchronous relative to CLK for Burst mode.



F-WE#

Flash Write Enable input



F-VCC

Flash device power supply (1.7 V to 1.95 V)



F-VCCQ

Flash Input/Output Buffer power supply



VSS

Ground

F-RDY

Flash ready output. Indicates the status of the Burst read. VOL = Data invalid, VOH = Data valid.



F-CLK

Flash Clock. The first rising edge of CLK in conjunction with AVD# low latches the address input

and activates burst mode operation. After the initial word is output, subsequent rising edges of

CLK increment the internal address counter. CLK should remain low during asynchronous

access.



F-AVD#

Flash Address Valid input. Indicates to device that the valid address is present on the address

inputs. VIL = For asynchronous mode, indicates valid address; for burst mode, causes starting

address to be latched on rising edge of CLK. VIH = Device ignores address inputs.



F-RST#

Flash hardware reset input. VIL= device resets and returns to reading array data.



F-VPP

Flash accelerated input. At VHH, accelerates programming; automatically places device in unlock

bypass mode. At VIL, disables all program and erase functions. Should be at VIH for all other

conditions.



D-Amax – D-A0

DRAM Address input



D-DQ15 – D-DQ0

DRAM Data input/output



D-CLK

DRAM System Clock



D-CE#

DRAM Chip Select



D-CKE

DRAM Clock Enable



D-BA1 – BA0

DRAM Bank Select



D-RAS#

DRAM Row Address Strobe



D-CAS#

DRAM Column Address Strobe



D-UDQM – D-LDQM DRAM Data Input Mask



D-WE#

DRAM Write Enable input



D-VCCQ

DRAM Input/Output Buffer power supply



D-VCC

DRAM device power supply



D-UDQS

DRAM Upper Data Strobe, output with read data and input with write data



D-LDQS

DRAM Lower Data Strobe, output with read data and input with write data



D-CLK#

DDR Clock for negative edge of CLK



RFU

Reserved for Future Use. No device internal signal is currently connected to the package

connector but there is potential future use for the connector for a signal. It is recommended to

not use RFU connectors for PCB routing channels so that the PCB may take advantage of future

enhanced features in compatible footprint devices.



Not Connected. No device internal signal is connected to the package connector nor is there any

future plan to use the connector for a signal. The connection may safely be used for routing space

for a signal on a Printed Circuit Board (PCB).



DNU

Do Not Use. A device internal signal may be connected to the package connector. The connection

may be used by Cypress for test or other purposes and is not intended for connection to any host

system signal. Any DNU signal related function will be inactive when the signal is at VIL. The

signal has an internal pull-down resistor and may be left unconnected in the host system or may

be tied to VSS. Do not use these connections for PCB signal routing channels. Do not connect

any host system signal to these connections.



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