TPS16632RGET datasheet(7/30 Pages) TI1

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TPS1663

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SLVSET9A – SEPTEMBER 2018 – REVISED OCTOBER 2018

Product Folder Links: TPS1663

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Electrical Characteristics (continued)

–40°C

≤ TA = TJ ≤ +125°C, 4.5 V < V(IN) = V(P_IN) < 60 V, V(SHDN) = 2 V, R(ILIM) = 30 kΩ, IMON = PGOOD = FLT = OPEN, C(OUT)

= 1 μF, C(dVdT) = OPEN. (All voltages referenced to GND, (unless otherwise noted))

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

R(PGOOD)

PGOOD Pull-down resistance

V(dVdT) = 0 V, I(PGOOD) = 5 mA sinking

130

I(PGOOD)

PGOOD Input leakage current

0 V

≤ V(PGOOD) ≤ 60 V

–100

100

THERMAL SHUT DOWN (TSD)

T(J_REG)

Thermal regulation set point

147

150

154

ºC

T(TSD)

TSD threshold, rising

164

ºC

T(TSDhyst)

TSD hysteresis

ºC

MODE

MODE_SEL

Mode selection

MODE = Open

Latch

MODE = Short to GND

Auto–R

etry

7.6 Timing Requirements

–40°C

≤ TA = TJ ≤ +125°C, 4.5 V < V(IN) = V(P_IN) < 60 V, V(SHDN) = 2 V, R(ILIM) = 30 kΩ, IMON = PGOOD = FLT = OPEN, C(OUT)

= 1 μF, C(dVdT) = OPEN. (All voltages referenced to GND, (unless otherwise noted))

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

UVLO INPUT (UVLO)

UVLO_ton(dly)

UVLO switch turnon delay

UVLO

↑ (100 mV above V(UVLOR)) to

V(OUT) = 100 mV

669 +

49564 x

C(dVdT)

µs

UVLO_toff(dly)

UVLO switch turnoff delay

UVLO

↓(20 mV below V(UVLOF)) to FLT↓

µs

OVER VOLTAGE PROTECTION INPUT (OVP)

tOVP(dly)

OVP switch turnOFF delay

OVP

↑ (20 mV above V(OVPR)) to FLT↓

µs

tOVP(dly)

OVP switch disable delay

OVP

↓ (100 mV below V(OVPF)) to FET

150 +

49564 x

C(dVdT)

µs

SHUTDOWN CONTROL INPUT (SHDN)

tSD(dly)

SHUTDOWN entry delay

SHDN

↓ (below V(SHUTF)) to FET OFF

0.9

µs

CURRENT LIMIT

tRCB_FLT(dly)

Hot-short response time

I(OUT) > I(SCP)

0.3

µs

Soft short response

I(FASTTRIP) < I(OUT) < I(SCP)

3.3

4.2

µs

tCL_PLIM(dly)

Maximum duration in current & (power

limiting: TPS16632 Only)

162

tCL_PLIM_FLT(dly)

FLT delay in current & (power limiting:

TPS16632 Only)

1.3

OUTPUT RAMP CONTROL (dVdT)

t(FASTCHARGE)

Output ramp time in fast charging

C(dVdT) = Open, 10% to 90%

V(OUT), C(OUT) = 1 µF;

240

µs

t(dVdT)

Output ramp time

C(dVdT) = 22 nF, 10% to 90% V(OUT)

8.35

POWER GOOD (PGOOD)

tPGOOD

PGOOD delay (deglitch)

Rising and falling edges

11.5

THERMAL SHUTDOWN (TSD)

t(TSD_retry)

Retry delay in TSD

MODE = GND

648

t(Treg_timeout)

Thermal Regulation Timeout

1.3

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