AD8139

Rev. A | Page 21 of 24

an amplitude of 2.5 V p-p and is swinging about ground. Using

the results in Equation 16, the common-mode voltage at the

this case is 0.2 V, which exceeds the lower input common-mode

voltage limit.

One way to avoid the input common-mode swing limitation is

swings from 1.25 V to 3.75 V, which is well within the

input common-mode voltage limits of the AD8139. Another

wasted common-mode current flows. Figure 60 illustrates how

to provide the low-Z bias voltage. For situations that do not

require a precise reference, a simple voltage divider will suffice

to develop the input voltage to the buffer.

0V TO 5V

AD8139

+

–

8

2

1

6

3

4

5

200

Ω

324

Ω

5V

200

Ω

324

Ω

0.1

µF

0.1

µF

10

µF

+

AD8031

+

–

0.1

µF

5V

ADR431

2.5V

REFERENCE

TO AD7674 REFBUFIN

Figure 60. Low-Z 2.5 V Buffer

Another way to avoid the input common-mode swing limita-

tion is to use dual power supplies on the AD8139. In this case,

the biasing circuitry is not required.

Bandwidth Versus Closed-Loop Gain

The AD8139’s 3 dB bandwidth decreases proportionally to

increasing closed-loop gain in the same way as a traditional

voltage feedback operational amplifier. For closed-loop gains

greater than 4, the bandwidth obtained for a specific gain can be

estimated as

)

300

(

,

3

,

MHz

R

R

R

V

dB

f

F

G

G

dm

OUT

×

+

=

−

(20)

or equivalently, β(300 MHz).

This estimate assumes a minimum 90 degree phase margin for

the amplifier loop, which is a condition approached for gains

greater than 4. Lower gains will show more bandwidth than

predicted by the equation due to the peaking produced by the

lower phase margin.

Estimating DC Errors

Primary differential output offset errors in the AD8139 are due

to three major components: the input offset voltage, the offset

feedback network resistances, and the offset produced by the dc

voltage difference between the input and output common-mode

voltages in conjunction with matching errors in the feedback

network.

The first output error component is calculated as

⎟

⎠

⎞

⎜

⎝

⎛

+

=

G

G

F

IO

R

R

R

V

e

Vo

1

_

(21)

AD8139 is laser trimmed and guaranteed to be less than 500 μV.

The second error is calculated as

( )

F

IO

G

F

F

G

G

G

F

IO

R

I

R

R

R

R

R

R

R

I

e

Vo

=

⎟

⎠

⎞

⎜

⎝

⎛

+

⎟

⎠

⎞

⎜

⎝

⎛

+

=

2

_

(22)

currents.

The third error voltage is calculated as

)

(

3

_

OCM

ICM

V

V

enr

e

Vo

−

×

∆

=

(23)

where Δenr is the fractional mismatch between the two

feedback resistors.

The total differential offset error is the sum of these three error

sources.

Other Impact of Mismatches in the Feedback Networks

The internal common-mode feedback network will still force

feedback networks are mismatched. The mismatch will,

however, cause a gain error proportional to the feedback

network mismatch.

Ratio-matching errors in the external resistors will degrade the

terminals, much the same as with a four-resistor difference

amplifier made from a conventional op amp. Ratio-matching

errors will also produce a differential output component that is

feedback factors (βs). In most applications using 1% resistors,

this component amounts to a differential dc offset at the output

that is small enough to be ignored.