AD8139

Rev. A | Page 22 of 24

Driving a Capacitive Load

A purely capacitive load will react with the bondwire and pin

inductance of the AD8139, resulting in high frequency ringing

in the transient response and loss of phase margin. One way to

minimize this effect is to place a small resistor in series with

each output to buffer the load capacitance, see Figure 6 and

Figure 61. The resistor and load capacitance will form a first-

order low-pass filter; therefore, the resistor value should be as

small as possible. In some cases, the ADCs require small series

resistors to be added on their inputs.

–13

–12

–11

–10

–9

–8

–7

–6

–5

–4

–3

–2

–1

0

1

2

3

4

10M

100M

1G

5

FREQUENCY (MHz)

Figure 61. Frequency Response for

Various Capacitive Load and Series Resistance

The Typical Performance Characteristics that illustrate transient

response versus the capacitive load were generated using series

resistors in each output and a differential capacitive load.

Layout Considerations

Standard high speed PCB layout practices should be adhered to

when designing with the AD8139. A solid ground plane is recom-

mended and good wideband power supply decoupling networks

should be placed as close as possible to the supply pins.

To minimize stray capacitance at the summing nodes, the

copper in all layers under all traces and pads that connect to the

summing nodes should be removed. Small amounts of stray

summing-node capacitance will cause peaking in the frequency

response, and large amounts can cause instability. If some stray

summing-node capacitance is unavoidable, its effects can be

compensated for by placing small capacitors across the feedback

resistors.

Terminating a Single-Ended Input

Controlled impedance interconnections are used in most high

speed signal applications, and they require at least one line

termination. In analog applications, a matched resistive

termination is generally placed at the load end of the line. This

section deals with how to properly terminate a single-ended

input to the AD8139.

The input resistance presented by the AD8139 input circuitry is

seen in parallel with the termination resistor, and its loading

effect must be taken into account. The Thevenin equivalent

circuit of the driver, its source resistance, and the termination

resistance must all be included in the calculation as well. An

exact solution to the problem requires the solution of several

simultaneous algebraic equations and is beyond the scope of

this data sheet. An iterative solution is also possible and simpler,

especially considering the fact that standard 1% resistor values

are generally used.

Figure 62 shows the AD8139 in a unity-gain configuration

driving the AD6645, which is a 14-bit high speed ADC, and

with the following discussion, provides a good example of how

to provide a proper termination in a 50 Ω environment.

resistance of the AD8139 circuit (calculated using Equation 19),

yields an overall input resistance of 50 Ω that is seen by the

signal source. In order to have matched feedback loops, each

equal to 228 Ω. The closest standard 1% value to 228 Ω is 226 Ω

achieved by using two resistors in series to obtain a resistance

closer to 228 Ω.

Things get more complicated when it comes to determining the

feedback resistor values. The amplitude of the signal source

when terminated in 50 Ω. Thus, a 2 V p-p terminated amplitude

when calculating the closed-loop gain because in the upper loop

tance looking back toward the source. The Thevenin voltage of

the signal source is greater than the signal source output voltage

than 50 Ω. In this case, it is 61.9 Ω and the Thevenin voltage

and resistance are 2.2 V p-p and 28 Ω, respectively. Now the

upper input branch can be viewed as a 2.2 V p-p source in series

with 228 Ω. Since this is a unity-gain application, a 2 V p-p

(2/2.2) = 206 Ω. The closest standard value to this is 205 Ω.

When generating the Typical Performance Characteristics data,

the measurements were calibrated to take the effects of the

terminations on closed-loop gain into account.