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AM6548 数据表(PDF) 76 Page - Texas Instruments |
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AM6548 数据表(HTML) 76 Page - Texas Instruments |
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76 / 299 page  76 AM6548, AM6528, AM6546 AM6526, AM6527 SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527 Terminal Configuration and Functions Copyright © 2017–2018, Texas Instruments Incorporated Table 4-27. GPMC0 Signal Descriptions (continued) SIGNAL NAME [1] DESCRIPTION [2] PIN TYPE [3] BALL [4] GPMC0_A27 GPMC address 27 in A/D non-multiplexed mode and Address 27 in A/D multiplexed mode OZ R25 GPMC0_AD0 GPMC Data 0 Input/Output in A/D non-multiplexed mode and additionally Address 1 Output in A/D multiplexed mode IO M27 GPMC0_AD1 GPMC Data 1 Input/Output in A/D non-multiplexed mode and additionally Address 2 Output in A/D multiplexed mode IO M23 GPMC0_AD2 GPMC Data 2 Input/Output in A/D non-multiplexed mode and additionally Address 3 Output in A/D multiplexed mode IO M28 GPMC0_AD3 GPMC Data 3 Input/Output in A/D non-multiplexed mode and additionally Address 4 Output in A/D multiplexed mode IO M24 GPMC0_AD4 GPMC Data 4 Input/Output in A/D non-multiplexed mode and additionally Address 5 Output in A/D multiplexed mode IO N24 GPMC0_AD5 GPMC Data 5 Input/Output in A/D non-multiplexed mode and additionally Address 6 Output in A/D multiplexed mode IO N27 GPMC0_AD6 GPMC Data 6 Input/Output in A/D non-multiplexed mode and additionally Address 7 Output in A/D multiplexed mode IO N28 GPMC0_AD7 GPMC Data 7 Input/Output in A/D non-multiplexed mode and additionally Address 8 Output in A/D multiplexed mode IO M25 GPMC0_AD8 GPMC Data 8 Input/Output in A/D non-multiplexed mode and additionally Address 9 Output in A/D multiplexed mode IO N23 GPMC0_AD9 GPMC Data 9 Input/Output in A/D non-multiplexed mode and additionally Address 10 Output in A/D multiplexed mode IO M26 GPMC0_AD10 GPMC Data 10 Input/Output in A/D non-multiplexed mode and additionally Address 11 Output in A/D multiplexed mode IO P28 GPMC0_AD11 GPMC Data 11 Input/Output in A/D non-multiplexed mode and additionally Address 12 Output in A/D multiplexed mode IO P27 GPMC0_AD12 GPMC Data 12 Input/Output in A/D non-multiplexed mode and additionally Address 13 Output in A/D multiplexed mode IO N26 GPMC0_AD13 GPMC Data 13 Input/Output in A/D non-multiplexed mode and additionally Address 14 Output in A/D multiplexed mode IO N25 GPMC0_AD14 GPMC Data 14 Input/Output in A/D non-multiplexed mode and additionally Address 15 Output in A/D multiplexed mode IO P24 GPMC0_AD15 GPMC Data 15 Input/Output in A/D non-multiplexed mode and additionally Address 16 Output in A/D multiplexed mode IO R27 GPMC0_BE0n_CLE GPMC Lower-Byte Enable (active low) or Command Latch Enable O T28 GPMC0_BE1n GPMC Upper-Byte Enable (active low) O P23 GPMC0_CSn0 GPMC Chip Select 0 (active low) O R24 GPMC0_CSn1 GPMC Chip Select 1 (active low) O T23 GPMC0_CSn2 GPMC Chip Select 2 (active low) O R25 GPMC0_CSn3 GPMC Chip Select 3 (active low) O T27 |
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