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AM6548 数据表(PDF) 1 Page - Texas Instruments |
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AM6548 数据表(HTML) 1 Page - Texas Instruments |
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1 / 299 page  Product Folder Order Now Technical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. AM6548, AM6528, AM6546 AM6526, AM6527 SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018 AM654x, AM652x Sitara™ Processors 1 Device Overview 1 1.1 Features 1 Processor Cores: • Quad-Core Arm® Cortex®-A53 Microprocessor Subsystem at up to 1.1 GHz – Two Dual-Core Cortex-A53 Clusters with 512KB L2 Cache Including SECDED – Each A53 Core has 32KB L1 ICache and 32K L1 DCache • Dual-Core Arm Cortex-R5F at up to 400 MHz – Supports Lockstep Mode – 16KB ICache, 16KB DCache, and 64KB RAM per R5F Core Industrial Subsystem: • Three Gigabit Industrial Communication Subsystems (PRU_ICSSG) – Two 10/100/1000 Ethernet Ports per PRU_ICSSG – Supports Two SGMII Ports (2) – Compatibility with 10/100Mb PRU-ICSS – 24× PWMs per PRU_ICSSG – Cycle-by-Cycle Control – Enhanced Trip Control – 18× Sigma-Delta Filters per PRU_ICSSG – Short Circuit Logic – Over-Current Logic – 6× Multi-Protocol Position Encoder Interfaces per PRU_ICSSG Memory Subsystem: • Up to 2MB of On-Chip L3 RAM with SECDED • Multi-Core Shared Memory Controller (MSMC) – Up to 2MB (2 banks × 1MB) SRAM with SECDED – Shared Coherent Level 2 or Level 3 Memory- Mapped SRAM – Shared Coherent Level 3 Cache – 256-Bit Processor Port Bus and 40-Bit Physical Address Bus – Coherent Unified Bi-Directional Interfaces to Connect to Processors or Device Masters – L2, L3 Cache Pre-Warming and Post Flushing – Bandwidth Management with Starvation Bound – One Infrastructure Master Interface – Single External Memory Master Interface – Supports Distributed Virtual System – Supports Internal DMA Engine – DRU (Data Routing Unit) – ECC Error Protection • DDR Subsystem (DDRSS) – Supports DDR3L/DDR4 Memory Types up to DDR-1600 – Supports LPDDR4 Memory Type up to DDR- 1333 – 32-Bit Data Bus and 7-Bit SECDED Bus – 32GB of Total Addressable Space • General-Purpose Memory Controller (GPMC) Safety: • AM65xx Helps System Designers Address Safety Requirements – The Dual Cortex-R5F System is Undergoing Assessment to be Certified at TÜV SÜD According to IEC 61508, Targeting SIL-3 – The A53 Cores and Entire System on Chip (SoC) is Undergoing Assessment to be Certified at TÜV SÜD According to IEC 61508, Targeting SIL-2 – ECC or Parity on Calculation-Critical Memories – ECC and Parity on Internal Bus Interconnect – Firewalls to Help Provide Freedom From Interference (FFI) – Built-In Self-Test (BIST) for CPU, High-End Timers, and On-Chip RAM – Hardware Error Injection Support for Test-for- Diagnostics – Error Signaling Modules (ESM) for Capture of Safety Related Errors – Voltage, Temperature, and Clock Monitoring – Windowed and Non-Windowed Watchdog Timers in Multiple Clock Domains • MCU Island – Isolation of the Dual-Core Arm Cortex-R5F Microprocessor Subsystem to Help Provide Freedom From Interference (FFI) – Separate Voltage, Clocks, Resets, and Dedicated Peripherals – Internal MCSPI Connection to the Rest of SoC Security: • Secure Boot Supported – Hardware-Enforced Root-of-Trust – Support to Switch Root-of-Trust via Backup Key – Support for Takeover Protection, IP Protection, and Anti-Roll Back Protection • Cryptographic Acceleration Supported – Session-Aware Cryptographic Engine with |
类似零件编号 - AM6548 |
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类似说明 - AM6548 |
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