U4256BM-RFS datasheet(7/19 Pages) ATMEL

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U4256BM-R

4562C–AUDR–08/04

DAC 1, 2 in AM Mode

(Pin 3 and Pin 4)

In AM mode the DAC input voltage V

(PDO) is internal connected to 3 V. The gains of

DAC1 and DAC2 have a range of 0.46

× 3V to 3.03 × 3V. V

(PDO) is the PLL tuning volt-

age output. This range is divided into 256 steps. So one step is approximately

(3.03 - 0.46)

× 3 V/255 = 0.01007 × 3 V. The gain of DAC1 can be controlled by the Bits

36 to 43 (G-20 to G-27) and the gain of DAC2 by the Bits 0 to 7 (G-20 to G-27) as

following:

Offset = 31 (intermediate position)

Remark: V

(PDO) is 3 V in AM mode.

The offset of DAC1 and DAC2 has a range of +1.46 V to -1.49 V. This range is divided

into 64 steps. So one step is approximately 2.95 V/ 63 = 46.8 mV. The offset DAC1 can

be controlled by the Bits 44 to 49 (O-20 to O-25) and the offset of DAC2 by the Bits 8 to

13 (O-2

0 to O-25) as following:

Gain = 53 (intermediate position)

Gain DAC1

Approximately

B43

B42

B41

B40

B39

B38

B37

B36

Decimal

Gain

Gain DAC2

Approximately

B7B6B5B4B3B2B1B0

Decimal

Gain

0.4607

× 3 V

00000000

0.4710

× 3 V

00000001

0.4812

× 3 V

00000010

0.4915

× 3 V

00000011

...

1.0029

× 3 V

00110101

...

3.0097

× 3 V

11111101

253

3.0196

× 3 V

11111110

254

3.0296

× 3 V

11111111

255

Offset DAC1

Approximately

B49

B48

B47

B46

B45

B44

Decimal

Gain

Offset DAC2

Approximately

B13

B12

B11

B10

Decimal

Gain

1.4606 V

000

1.4138 V

000

001

1.3665 V

000

010

1.3196 V

000

011

...

-0.0079 V

011

111

...

-1.3975 V

111

101

-1.4447 V

111

110

-1.4917 V

111

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