11

U4256BM-R

4562C–AUDR–08/04

Application Information

Figure 13. FMOSCIN Sensitivity

3-wire Bus

Description

The register settings of U4256BM-R are programmed by a 3-wire bus protocol. The bus

protocol consists of separate commands. A defined number of bits is transmitted

sequentially during each command.

One command is used to program all the bits of one register. The different registers

available (see table Data Transfer) are addressed by the length of the command (num-

ber of transmitted bits) and by two address bits, that are unique to each register of a

given length. 16-bit registers are programmed by 16-bit commands and 24-bit registers

are programmed by 24-bit commands.

Each bus command starts with a rising edge on the enable line (EN) and ends with a

falling edge on EN. EN has to be kept HIGH during the bus command.

The sequence of transmitted bits during one command starts with the LSB of the first

byte and ends with the MSB of the last byte of the register addressed. To transmit one

bit (0/1) DATA has to be set to the appropriate value (LOW/HIGH) and a LOW to HIGH

transition has to be performed on the clock line (CLK) while DATA is valid. The DATA is

evaluated at the rising edges of CLK. The number of LOW to HIGH transitions on CLK

during the HIGH period of EN is used to determine the length of the command.

The bus protocol and the register addressing of U4256BM-R are compatible to the

addressing used in U4255BM and T4258. That means U4256BM-R and U4255BM (or

T4258) can be operated on the same 3-wire bus as shown in the application circuit.

0

50

100

150

0

20

40

60

80

100

120

140

160

Frequency (MHz)

Vi (mV