U4256BM-RFS datasheet(6/19 Pages) ATMEL

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U4256BM-R

4562C–AUDR–08/04

DAC 1, 2 in FM Mode

(Pin 3 and Pin 4)

The gains of DAC1 and DAC2 have a range of 0.69

× V

(PDO) to 2.16 × V(PDO). V(PDO) is

the PLL tuning voltage output. This range is divided into 256 steps. So one step is

approximately (2.16 - 0.46)

× V

(PDO) / 255 = 0.005764 × V(PDO). The gain of DAC1 can be

controlled by the Bits 36 to 43 (G-20 to G-27) and the gain of DAC2 by the Bits 0 to 7 (G-

20 to G-27) as following:

Offset = 31 (intermediate position)

The offset of DAC1 and DAC2 has a range of 0.56 V to -0.59 V. This range is divided

into 64 steps. So one step is approximately 1.15 V/ 63 = 18.25 mV. The offset DAC1

can be controlled by the Bits 44 to 49 (O-20 to O-25) and the offset of DAC2 by the Bits 8

to 13 (O-20 to O-25) as following:

Gain = 53 (intermediate position)

Gain DAC1

Approximately

B43

B42

B41

B40

B39

B38

B37

B36

Decimal

Gain

Gain DAC2

Approximately

B7B6

B5B4B3B2

B1B0

Decimal

Gain

0.69

× V

(PDO)

0000

000

0.69576

× V

(PDO)

0000

001

0.70153

× V

(PDO)

0000

010

0.70729

× V

(PDO)

0000

011

...

0.99549

× V

(PDO)

0110

101

...

2.14847

× V

(PDO)

1111

101

253

2.15424

× V

(PDO)

1111

110

254

2.16

× V

(PDO)

1111

111

255

Offset DAC1

Approximately

B49

B48

B47

B46

B45

B44

Decimal

Gain

Offset DAC2

Approximately

B13

B12

B11

B10

Decimal

Gain

0.56 V

000

0.5417 V

000

001

0.5235 V

000

010

0.5052 V

000

011

...

+0.0059 V

...

0.5535 V

111

101

-0.5717 V

111

110

-0.59 V

111

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