AM29F004B datasheet(19/37 Pages) AMD

19 / 37 page

8/5/05

Am29F004B

AD VA NC E

IN FO RM AT ION

WRITE OPERATION STATUS

The device provides several bits to determine the status of a

write operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 6 on

page 19 and the following subsections describe the functions

of these bits. DQ7 and DQ6 each offer a method for deter-

mining whether a program or erase operation is complete or

in progress. These three bits are discussed first.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system

whether an Embedded Algorithm is in progress or completed,

or whether the device is in Erase Suspend. Data# Polling is

valid after the rising edge of the final WE# pulse in the

program or erase command sequence.

During the Embedded Program algorithm, the device outputs

on DQ7 the complement of the datum programmed to DQ7.

This DQ7 status also applies to programming during Erase

Suspend. When the Embedded Program algorithm is com-

plete, the device outputs the datum programmed to DQ7. The

system must provide the program address to read valid status

information on DQ7. If a program address falls within a pro-

tected sec t or, Data# Po lling on DQ7 is active fo r

approximately 2 µs, then the device returns to reading array

data.

During the Embedded Erase algorithm, Data# Polling pro-

duces a “0” on DQ7. When the Embedded Erase algorithm is

complete, or if the device enters the Erase Suspend mode,

Data# Polling produces a “1” on DQ7. This is analogous to

the complement/true datum output described for the

Embedded Program algorithm: the erase function changes

all the bits in a sector to “1”; prior to this, the device outputs

the “complement,” or “0.” The system must provide an

address within any of the sectors selected for erasure to read

valid status information on DQ7.

After an erase command sequence is written, if all sectors

selected for erasing are protected, Data# Polling on DQ7 is

active for approximately 100 µs, then the device returns to

reading array data. If not all selected sectors are protected,

the Embedded Erase algorithm erases the unprotected sec-

tors, and ignores the selected sectors that are protected.

When the system detects DQ7 changes from the comple-

ment to true data, it can read valid data at DQ7–DQ0 on the

following read cycles. This is because DQ7 may change

asynchronously with DQ0–DQ6 while Output Enable (OE#) is

asserted low. The Data# Polling Timings (During Embedded

Algorithms) figure in the AC Characteristics on page 24

section illustrates this.

Table 6 on page 19 shows the outputs for Data# Polling on

DQ7. Figure 5, on page 17 shows the Data# Polling

algorithm.

Notes:

VA = Valid address for programming. During a sector erase

operation, a valid address is an address within any sector

selected for erasure. During chip erase, a valid address is any

non-protected sector address.

DQ7 should be rechecked even if DQ5 = “1” because DQ7 may

change simultaneously with DQ5.

Figure 5.

Data# Polling Algorithm

DQ7 = Data?

Yes

DQ5 = 1?

Yes

FAIL

PASS

Read DQ7–DQ0

Addr = VA

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

START

AM29F004B 数据表(PDF) 19 Page - Advanced Micro Devices

AM29F004B 数据表(HTML) 19 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

数据表下载