AM29F004B datasheet(4/37 Pages) AMD

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Am29F004B

8/5/05

AD VA NC E

IN FO RM AT ION

GENERAL DESCRIPTION

The Am29F004B is a 4 Mbit, 5.0 volt-only Flash memory

device organized as 524,288 bytes. The data appears on

DQ0–DQ7. The device is offered in a 32-pin PLCC package.

This device is designed to be programmed in-system with the

standard system 5.0 volt VCC supply. A 12.0 volt VPP is not

required for program or erase operations. The device can also

be programmed in standard EPROM programmers.

The device offers access times of 70, 90, and 120 ns, allowing

high speed microprocessors to operate without wait states.

To eliminate bus contention each device has separate chip

enable (CE#), write enable (WE#) and output enable (OE#)

controls.

Each device requires only a single 5.0 volt power supply for

both read and write functions. Internally generated and regu-

lated voltages are provided for the program and erase

operations.

The Am29F004B is entirely command set compatible with the

JEDEC single-power-supply Flash standard. Commands

are written to the command register using standard micropro-

cessor write timing. Register contents serve as inputs to an

internal state-machine that controls the erase and program-

ming circuitry. Write cycles also internally latch addresses

and data needed for the programming and erase operations.

Reading data out of the device is similar to reading from other

Flash or EPROM devices.

Device programming occurs by executing the program

command sequence. This initiates the Embedded Program

algorithm-an internal algorithm that automatically times the

program pulse widths and verifies proper cell margin.

Device erasure occurs by executing the erase command

sequence. This initiates the Embedded Erase algorithm–an

internal algorithm that automatically preprograms the array (if it

is not already programmed) before executing the erase opera-

tion. During erase, the device automatically times the erase

pulse widths and verifies proper cell margin.

The host system can detect whether a program or erase

operation is complete by reading the DQ7 (Data# Polling), or

DQ6 (toggle) status bits. After a program or erase cycle is

completed, the device is ready to read array data or accept

another command.

The sector erase architecture allows memory sectors to be

erased and reprogrammed without affecting the data con-

tents of other sectors. The device is fully erased when

shipped from the factory.

Hardware data protection measures include a low VCC

detector that automatically inhibits write operations during

power transitions.

The hardware sector protection feature dis-

ables both program and erase operations in any combination

of sectors of memory. This can be achieved in-system or via

programming equipment.

The Erase Suspend feature enables the user to put erase on

hold for any period of time to read data from, or program data

to, any sector that is not selected for erasure. True back-

ground erase can thus be achieved.

The device offers a standby mode as a power-saving fea-

ture. Once the system places the device into the standby

mode power consumption is greatly reduced.

AMD’s Flash technology combines years of Flash memory

manufacturing experience to produce the highest levels of

quality, reliability and cost effectiveness. The device electri-

cally erases all bits within a sector simultaneously via Fowler-

Nordheim tunnelling. The data is programmed using hot elec-

tron injection.

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