AM29F004B datasheet(16/37 Pages) AMD

16 / 37 page

Am29F004B

8/5/05

AD VA NC E

IN FO RM AT ION

cycles, followed by the program set-up command. The

program address and data are written next, which in turn ini-

tiate the Embedded Program algorithm. The system is not

required to provide further controls or timings. The device

automatically provides internally generated program pulses

and verify the programmed cell margin. (Note that if the

device is in the temporary sector unprotect mode, the byte

program command sequence only requires two cycles.) The

Command Definitions table shows the address and data

requirements for the byte program command sequence.

When the Embedded Program algorithm is complete, the

device then returns to reading array data and addresses are

no longer latched. The system can determine the status of

the program operation by using DQ7 or DQ6. See Write

Operation Status on page 17 for information on these status

bits.

Any commands written to the device during the Embedded

Program Algorithm are ignored. The Sector Erase command

sequence should be reinitiated once the device returns to

reading array data, to ensure data integrity.

Programming is allowed in any sequence and across sector

boundaries. A bit cannot be programmed from a 0 back to

a 1. Attempting to do so may halt the operation and set DQ5

to 1, or cause the Data# Polling algorithm to indicate the oper-

ation was successful. However, a succeeding read shows

that the data is still 0. Only erase operations can convert a 0

to a 1”.

Note: See the appropriate Command Definitions table for program

command sequence.

Figure 3.

Program Operation

Chip Erase Command Sequence

Chip erase is a six-bus-cycle operation. The chip erase

command sequence is initiated by writing two unlock cycles,

followed by a set-up command. Two additional unlock write

cycles are then followed by the chip erase command, which

in turn invokes the Embedded Erase algorithm. The device

does not require the system to preprogram prior to erase. The

Embedded Erase algorithm automatically preprograms and

verifies the entire memory for an all zero data pattern prior to

electrical erase. The system is not required to provide any

controls or timings during these operations. (Note that if the

device is in the temporary sector unprotect mode, the chip

erase command sequence only requires four cycles.) The

Command Definitions table shows the address and data

requirements for the chip erase command sequence.

Any commands written to the chip during the Embedded

Erase algorithm are ignored. The Sector Erase command

sequence should be reinitiated once the device returns to

reading array data, to ensure data integrity.

The system can determine the status of the erase operation

by using DQ7, DQ6, or DQ2. See Write Operation Status on

page 17 for information on these status bits. When the

Embedded Erase algorithm is complete, the device returns to

reading array data and addresses are no longer latched.

Figure 4, on page 15 illustrates the algorithm for the erase

operation. See the Erase/Program Operations on page 25

for parameters, and to Figure 12, on page 26 for timing

waveforms.

Sector Erase Command Sequence

Sector erase is a six-bus-cycle operation. The sector erase

command sequence is initiated by writing two unlock cycles,

followed by a set-up command. Two additional unlock write

cycles are then followed by the address of the sector to be

erased, and the sector erase command. (Note that if the

device is in the temporary sector unprotect mode, the sector

erase command sequence only requires four cycles.) The

Command Definitions table shows the address and data

requirements for the sector erase command sequence.

The device does not require the system to preprogram the

memory prior to erase. The Embedded Erase algorithm auto-

matically programs and verifies the sector for an all zero data

pattern prior to electrical erase. The system is not required to

provide any controls or timings during these operations.

After the command sequence is written, a sector erase time-

out of 50 µs begins. During the time-out period, additional

sector addresses and sector erase commands may be

written. Loading the sector erase buffer may be done in any

sequence, and the number of sectors may be from one sector

to all sectors. The time between these additional cycles must

be less than 50 µs, otherwise the last address and command

might not be accepted, and erasure may begin. It is recom-

mended that processor interrupts be disabled during this time

to ensure all commands are accepted. The interrupts can be

re-enabled after the last Sector Erase command is written. If

the time between additional sector erase commands can be

assumed to be less than 50 µs, the system need not monitor

DQ3. Any command other than Sector Erase or Erase

Suspend during the time-out period resets the device to

reading array data. The system must rewrite the command

START

Write Program

Command Sequence

Data Poll

from System

Verify Data?

Yes

Last Address?

Yes

Programming

Completed

Increment Address

Embedded

Program

algorithm

in progress

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