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71321LA55PFG 数据表(PDF) 14 Page - Integrated Device Technology |
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71321LA55PFG 数据表(HTML) 14 Page - Integrated Device Technology |
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14 / 18 page ![]() 6.42 IDT71321SA/LA and IDT71421SA/LA High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges 14 Timing Waveform of Interrupt Mode(1) Se t INT Cle a r INT NOTES: 1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”. 2. See Interrupt Truth Table. 3. Timing depends on which enable signal (CE or R/W) is asserted last. 4. Timing depends on which enable signal (CE or R/W) is de-asserted first. AC Ele c t ric a l Cha ra c t e rist ic s Ove r t he Ope rat ing Te m pe ra t ure Supply Volt a ge Ra nge (1) NOTE: 1. 'X' in part numbers indicates power rating (SA or LA). tINS ADDR"A" INT"B" INTERRUPT ADDRESS tWC tAS R/W"A" tWR 2691 drw 14 (3) (3) (2) (4) tRC INTERRUPT CLEAR ADDRESS ADDR"B" OE"B" tINR INT"B" 2691 drw 15 tAS(3) (3) (2) , 71321X35 71421X35 Com'l Only 71321X55 71421X55 Com'l & Ind Symbol Parameter Min.Max.Min.Max. Unit INTERRUPT TIMING tAS Address Set-up Time 0 ____ 0 ____ ns tWR Write Recovery Time 0 ____ 0 ____ ns tINS Interrupt Set Time ____ 25 ____ 45 ns tINR Interrupt Reset Time ____ 25 ____ 45 ns 2691 tbl 11b |
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