©2018 Integrated Device Technology, Inc.

FEBRU ARY 2 0 1 8

DSC-2691/16

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HIGH SPEED

2K X 8 DUAL-PORT

STATIC RAM

WITH INTERRUPTS

IDT71321SA/LA

IDT71421SA/LA

Features

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High-speed access

– Commercial: 20/25/35/55ns (max.)

– Industrial: 25/55ns (max.)

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Low-power operation

– IDT71321/IDT71421SA

– IDT71321/421LA

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Two INT flags for port-to-port communications

Func t iona l Bloc k Dia gra m

NOTES:

1.

IDT71321(MASTER): BUSYisopendrainoutputandrequirespullupresistorof270

Ω.

IDT71421 (SLAVE): BUSY is input.

2. Open drain output: requires pullup resistor of 270

Ω.

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MASTER IDT71321 easily expands data bus width to 16-or-

more-bits using SLAVE IDT71421

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On-chip port arbitration logic (IDT71321 only)

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BUSY output flag on IDT71321; BUSY input on IDT71421

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Fully asynchronous operation from either port

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Battery backup operation – 2V data retention (LA only)

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TTL-compatible, single 5V ±10% power supply

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Available in 52-Pin PLCC, 52-Pin STQFP, 64-Pin TQFP, and

64-Pin STQFP

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Industrial temperature range (–40°C to +85°C) is available

for selected speeds

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Green parts available, see ordering information

I/O

Control

Address

Decoder

MEMORY

ARRAY

ARBITRATION

and

INTERRUPT

LOGIC

Address

Decoder

I/O

Control

2691 drw 01

(2)

(1,2)

(1,2)

(2)

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LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018