6.42

IDT71321SA/LA and IDT71421SA/LA

High Speed 2K x 8 Dual-Port Static RAM with Interrupts

Industrial and Commercial Temperature Ranges

16

beingexpandedindepth,thentheBUSYindicationfortheresultingarray

does not require the use of an external AND gate.

Widt h Ex pa nsion w it h Busy Logic

M a st e r/Slave Ar ra ys

WhenexpandinganSRAMarrayinwidthwhileusingBUSYlogic,one

master part is used to decide which side of the SRAM array will receive

a BUSY indication, and to output that indication. Any number of slaves to

be addressed in the same address range as the master, use the BUSY

signal as a write inhibit signal. Thus on the IDT71321/IDT71421 SRAMs

the BUSY pin is an output if the part is Master (IDT71321), and theBUSY

pin is an input if the part is a Slave (IDT71421) as shown in Figure 3.

Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit

decision could result with one master indicating BUSY on one side of the

arrayandanothermasterindicatingBUSY ononeothersideofthearray.

Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand

inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.

The BUSY arbitration, on a Master, is based on the chip enable and

address signals only. It ignores whether an access is a read or write. In

a master/slave array, both address and chip enable must be valid long

enoughforaBUSYflagtobeoutputfromthemasterbeforetheactualwrite

pulsecanbeinitiatedwitheithertheR/Wsignalorthebyteenables. Failure

toobservethistimingcanresultinaglitchedinternalwriteinhibitsignaland

corrupted data in the slave.

Func t iona l De sc ript ion

The IDT71321/IDT71421 provides two ports with separate control,

address and I/O pins that permit independent access for reads or writes

to any location in memory. The IDT71321/IDT71421 has an automatic

power down feature controlled by CE. The CE controls on-chip power

down circuitry that permits the respective port to go into a standby mode

memory array is permitted.

I nt e r rupt s

Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox

or message center) is assigned to each port. The left port interrupt flag

II.Theleftportclearstheinterruptbyaccessingaddresslocation7FEwhen

memorylocation7FF.Themessage(8bits)at7FEor7FFisuser-defined,

sinceitisanaddressableSRAMlocation.Iftheinterruptfunctionisnotused,

address locations 7FE and 7FF are not used as mail boxes, but as part

of the random access memory. Refer to Truth Table II for the interrupt

operation.

Busy Logic

BusyLogicprovidesahardwareindicationthatbothportsoftheRAM

haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe

twoaccessestoproceedandsignalstheothersidethattheRAMis“Busy”.

The BUSY pin can then be used to stall the access until the operation on

the other side is completed. If a write operation has been attempted from

thesidethatreceivesabusyindication,thewritesignalisgatedinternally

to prevent the write from proceeding.

Theuseof BUSYLogicisnotrequiredordesirableforallapplications.

InsomecasesitmaybeusefultologicallyORthe BUSYoutputstogether

and use any BUSY indication as an interrupt source to flag the event of

anillegalorillogicaloperation.InslavemodetheBUSYpinoperatessolely

asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying

the BUSY pins HIGH. If desired, unintended write operations can be

prevented to a port by tying the BUSY pin for that port LOW.

The BUSY outputs on the IDT71321 (Master) are open drain type

outputs and require open drain resistors to operate. If these SRAMs are

Figure 3. Busy and chip enable routing for both width and depth

expansion with IDT71321 (Master) and (Slave) IDT71421 SRAMs.

2691 drw 16

MASTER

Dual Port

SRAM

CE

MASTER

Dual Port

SRAM

CE

SLAVE

Dual Port

SRAM

CE

SLAVE

Dual Port

SRAM

CE

5V

5V

270

Ω

270

Ω