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74FCT16952CTPVG 数据表(PDF) 6 Page - Integrated Device Technology |
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74FCT16952CTPVG 数据表(HTML) 6 Page - Integrated Device Technology |
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6 / 7 page ![]() 6 INDUSTRIALTEMPERATURERANGE IDT74FCT16952AT/CT/ET FASTCMOS16-BITREGISTEREDTRANSCEIVER Pulse Generator RT D.U.T. V CC VIN CL VOUT 50pF 500 Ω 500 Ω 7.0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL tSU tH tREM tSU tH PRESET CLEAR CLOCK ENABLE ETC. HIGH-LOW-HIGH PULSE LOW-HIGH-LOW PULSE tW 1.5V 1.5V SAME PHASE INPUT TRANSITION 3V 1.5V 0V 1.5V VOH tPLH OUTPUT OPPOSITE PHASE INPUT TRANSITION 3V 1.5V 0V tPLH tPHL tPHL VOL CONTROL INPUT 3V 1.5V 0V 3.5V 0V OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED SWITCH OPEN VOL 0.3V 0.3V tPLZ tPZL tPZH tPHZ 3.5V 0V 1.5V 1.5V ENABLE DISABLE VOH T EST CI RCU I T S AN D WAV EFORM S Propagation Delay Test Circuits for All Outputs Enable and Disable Times Set-up, Hold, and Release Times Pulse Width NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. Test Switch Open Drain Disable Low Closed Enable Low All Other Tests Open SWI TCH POSI T I ON DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. |
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