DA6510.009

6 September, 2018

3 (32)

FUNCTIONAL DESCRIPTION

In battery operated applications the VDD of the

MAS6510 can vary along with battery capacity. In

such case the VDD level monitoring feature can be

useful to indicate battery level, help choosing

between different power modes in the system or

even using measured VDD level for compensating

VDD dependencies. In the VDD level monitoring

mode the on-chip regulator has to be disabled.

Communication with MAS6510 is handled by the

serial interface compatible with either a bi-directional

2-wire I2C bus or a 4-wire SPI bus. The XSPI pin is

for selecting which bus type is used.

Note: The 2-wire I2C bus of MAS6510 supports only

basic I2C bus communication protocol but not for

example 10-bit addressing, arbitration and clock

stretching features of the I2C bus specification.

The XCLR pin can be used to hard reset the device

including the serial communication. Device reset is

possible also via serial bus using the reset register.

Connecting VDD triggers internal power on reset

(POR) circuit which resets the device.

Despite of on chip power on reset (POR) circuit it is

recommended to reset the device manually after

every power up to guarantee proper register settings

after any VDD rise conditions.

The EOC pin indicates if a conversion has finished

and the result is ready to be read from the memory

via the serial interface. Using the EOC signal is not

necessary since it is alternatively possible to wait at

least maximum conversion time period before

reading out the result.

ABSOLUTE MAXIMUM RATINGS

All Voltages with Respect to Ground

Parameter

Symbol

Conditions

Min

Max

Unit

Supply Voltage

-0.3

5.0

V

Voltage Range for All Pins

-0.3

V

Latch-Up Current Limit

For all pins, test according

to JESD78A.

-100

+100

mA

Junction Temperature

+ 150

°C

Storage Temperature

Note 1

- 55

+125

°C

ESD Rating

Note 2

±1

kV

Note 3

±500V

V

Note: The absolute maximum rating values are stress ratings only. Functional operation of the device at conditions between maximum operating

conditions and absolute maximum ratings is not implied and EEPROM contents may be corrupted. Exposure to these conditions for extended

periods may affect device reliability (e.g. hot carrier degradation, oxide breakdown). Applying conditions above absolute maximum ratings may

be destructive to the devices.

Note: This is a CMOS device and therefore it should be handled carefully to avoid any damage by static voltages (ESD).

Note 1: See EEPROM memory data retention at hot temperature. Storage or bake at hot temperatures will reduce wafer level trimming and

calibration data retention time.

Note 2: JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.

Note 3: JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

RECOMMENDED OPERATION CONDITIONS

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

Supply Voltage

Capacitance and VDD level

monitoring modes

Note 1

1.8

2.7

3.6

V

Temperature mode

Note 1

1.9

2.7

3.6

V

Operating Temperature

-40

+25

+85

°C

EEPROM Write

Temperature

Note 2

+10

+25

+40

°C

Note 1. In capacitance measurement and VDD level monitoring the regulator must be disabled (TEMPREGEN=0) which allows operation down

to 1.8V. In temperature measurement the typ 1.8V regulator has to be enabled (TEMPREGEN=1) which limits the minimum supply voltage

down to 1.9V.

Note 2: EEPROM write operation is recommended to be done at room temperature