MAS6510 datasheet(13/32 Pages) MAS

13 / 32 page

DA6510.009

6 September, 2018

13 (32)

INTERNAL CS AND CR CAPACITOR MATRIX REGISTERS (E3/63HEX AND E4/64HEX)

There are two internal capacitor matrices CS_INT and

CR_INT that add capacitance in parallel to external

sensor capacitor (CS_EXT) and external reference

capacitor (CR_EXT) respectively. See application

figure 9 on page 30. These offset capacitances are

used to adjust the sensor signal to an optimal CDC

input range. Each capacitor matrix has a selectable

capacitance from 0pF up to 22pF in typical 86.3fF

steps. The three sigma process variation of the

capacitor matrix capacitance is ±10%.

The CS_INT capacitor matrix is controlled by 8-bit

has a corresponding EEPROM address (C3/43HEX)

as non-volatile storage of the trim value. The CR_INT

capacitor matrix is controlled by 8-bit register

(E4/64HEX) value OCDACR. See table 5. It has also

corresponding EEPROM address (C4/44HEX) as non-

volatile storage of the trim value. The internal CS_INT

and CR_INT capacitor matrix capacitance values

depend on OCDACS and OCDACR register values

according to equations 1-2.

After finding suitable CS_INT and CR_INT capacitor

matrix register values the trim values can be stored

the

corresponding

non-volatile

EEPROM

addresses.

In normal operating mode these trim values are

automatically read from the EEPROM during each

conversion start. See also table 10 Trimming control

255

OCDACS

INT



Equation 1.

255

OCDACR

INT



Equation 2.

Table 4. CS_INT internal capacitor matrix register (E3/63HEX), EEPROM address (C3/43HEX)

Bit Number

Bit Name

Description

Value

Function

7-0

OCDACS

CDAC control bits

00HEX

…FFHEX

CS_INT offset trimming

Table 5. CR_INT internal capacitor matrix register (E4/64HEX), EEPROM address (C4/44HEX)

Bit Number

Bit Name

Description

Value

Function

7-0

OCDACR

CDAC control bits

00HEX

…FFHEX

CR_INT offset trimming

GAIN REGISTER (E5/65HEX)

The 8-bit gain register (E5/65HEX) value (GRDAC)

adjusts excitation signal level for the capacitive

sensor.

See

table

Larger

value

corresponds to smaller input changing capacitance

range and vice versa. The gain register together with

the CS_INT and the CR_INT capacitor matrix trim

parameters define input capacitance range of

measurement. Ideally the sensor signal is fit

perfectly within the linear input capacitance range of

the CDC. Such trimming maximizes resolution and

dynamic range of the measurement.

The gain register (E5/65HEX) has a corresponding

EEPROM

address

(C5/45HEX)

non-voltage

storage of the trim value. After finding a suitable gain

EEPROM memory. In normal operating mode the

gain trim value is read automatically from the

EEPROM during each conversion start.

Table 6. Gain register (E5/65HEX), EEPROM address (C5/45HEX)

Bit Number

Bit Name

Description

Value

Function

7-0

GRDAC

RDAC control bits

00HEX

…FFHEX Gain adjustment by sensor excitation

signal level control

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