10 (14)

DA6181B.003

17 September, 2014

PIN CONFIGURATION & TOP MARKING FOR PLASTIC TSSOP-16 PACKAGE

QO2

VDD

QO1

QI

AGC

PDN2

OUT

RFIM

VSS

RFI2

RFIP

PDN1

AON

DEC

Top Marking Definitions:

z = Version Number

YYWW = Year Week

PIN DESCRIPTION

Pin Name

Pin

Type

Function

Note

VDD

1

P

Positive Power Supply

QO2

2

AO

Quartz Filter Output for Crystal 2

QO1

3

AO

Quartz Filter Output for Crystal 1

4

NC

1

QI

5

AI

Quartz Filter Input for Crystal and External

Compensation Capacitor

AGC

6

AO

AGC Capacitor

PDN2

7

DI

Power Down/Frequency Selection Input 2

2

OUT

8

DO

Receiver Output

3

DEC

9

AO

Demodulator Capacitor

AON

10

DI

AGC On Control

4

PDN1

11

DI

Power Down/Frequency Selection Input 1

2

12

NC

1

RFIP

13

AI

Positive Receiver Input

5

RFIM

14

AI

Negative Receiver Input

5

RFI2

15

AI

Receiver Input 2 (for Antenna Capacitor 2)

VSS

16

G

Power Supply Ground

A = Analog, D = Digital, P = Power, G = Ground, I = Input, O = Output, NC = Not Connected

Notes:

1) Pin 4 between QOM and QI must be connected to IC’s filtered VDD (pin 1) to eliminate TSSOP package

lead frame parasitic capacitances disturbing the crystal filter performance and minimizing noise coupling. All

other NC (Not Connected) type pins are recommended to be connected to VSS.

2) PDN1 = VDD and PDN2 = VDD means receiver off

-

Fast start-up is triggered when the receiver is after power down controlled to power on

3) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced

(modulated)

-

-

At power down the output is pulled to VSS (pull down switch)

4) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (normal operation)

-

Unused AON pad can be left unconnected due to internal pull-up with current < 1 µA. Pull up current is

switched off at power down.

5) Receiver inputs RFIP and RFIM have both 1.4 MΩ biasing resistors towards VDD