8 (20)

DA6116.010

5 October, 2017

REGISTER DESCRIPTION

Register

Address Byte

Data Byte

7

6

5

4

3

2

1

0

msb…lsb

Function

Write Operation Status

CR6

X

1

0

1

0

R

X

X

Output code

00000000

00000001

00000010

00000011

Both channels ready

Right channel busy

Left channel busy

Both channels busy

Peak Detector Status

CR4

X

1

0

1

1

R

X

X

Output code

00000000

00000001

00000010

00000011

No overload

Right overload

Left overload

Both overload

Peak Detector

Reference

CR3

X

1

1

0

0

R/W

X

X

Input code

11111111

11111110

11111101

•

•

00000010

00000001

00000000

DAC output, Note 1.

VREF(255)

VREF(254)

VREF(253)

•

•

VREF(2)

VREF(1)

VREF(0)

Left Channel Gain

CR2

X

1

1

0

1

R/W

X

X

Input code

11111111

11111110

11111101

•

•

11100000

00000010

00000001

00000000

Gain dB

+15.5

+15.0

+14.5

•

•

0.0

-111.0

-111.5

Mute

Right Channel Gain

CR1

X

1

1

1

0

R/W

X

X

Input code

11111111

11111110

11111101

•

•

11100000

00000010

00000001

00000000

Gain dB

+15.5

+15.0

+14.5

•

•

0.0

-111.0

-111.5

Mute

Test Mode, CR5

X

1

1

1

1

R/W

X

X

Reserved

Normal Write, Both

X

1

0

0

1

W

X

X

Write to both gain registers

Instant Write, Left (CR2)

X

0

1

0

1

W

X

X

Instant gain set to left channel

Instant Write, Right

(CR1)

X

0

1

1

0

W

X

X

Instant gain set to right channel

Instant Write, Both

X

0

1

1

1

W

X

X

Instant gain set to both channels

Note 1. Reference voltage is calculated from VREF =

(0.0036 + 0.0145 • CODE) • AVCC

Address byte bits:

•

Bit 2 is read/write bit (1=read, 0=write).

•

Bits marked as X are

don’t care bits.

•

The instant write commands write values to CR1 and CR2 registers for right and left channels respectively. These values can be read by

using the specified read commands for CR1 and CR2 registers.

Data byte bits:

•

•