CF52012 datasheet(30/48 Pages) INTEL

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Operation

Operation Code(14)

Address Bytes

Dummy Clock

Cycles

Data Bytes

DCLK fMAX

(MHz)

Extended dual input fast

write bytes

D2h

3 or 4

1 to 256(17)

100

Extended quad input fast

write bytes for EPCQ16,

EPCQ32, EPCQ64,

EPCQ128 and EPCQ256

devices

12h

3 or 4

1 to 256(17)

100

Extended quad input fast

write bytes for

EPCQ512/A devices

38h

3 or 4

1 to 256(17)

100

Erase bulk

C7h

100

Erase sector

D8h

3 or 4

100

Erase subsector

20h

100

4BYTEADDREN(18)

B7h

100

4BYTEADDREX(18)

E9h

100

1.7.1. 4BYTEADDREN and 4BYTEADDREX Operations (B7h and E9h)

To enable 4BYTEADDREN or 4BYTEADDREX operations, you can select the device by

driving the nCS signal low, followed by shifting in the operation code through DATA0.

Note:

You must execute a write enable operation before you can enable the 4BYTEADDREN

or 4BYTEADDREX operation.

Figure 6.

4BYTEADDREN Timing Diagram

Operation Code (B7h)

nCS

DCLK

DATA0

3 4

5 6

(14) List MSB first and LSB last.

(18) This operation is applicable for EPCQ256 and EPCQ512/A devices only.

1. Quad-Serial Configuration (EPCQ) Devices Datasheet

CF52012 | 2018.06.01

Quad-Serial Configuration (EPCQ) Devices Datasheet

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