CF52012 datasheet(35/48 Pages) INTEL

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Table 32.

EPCQ Device Identification

EPCQ Device

Silicon ID (Binary Value)

EPCQ16

b'0001 0101

EPCQ32

b'0001 0110

EPCQ64

b'0001 0111

EPCQ128

b'0001 1000

EPCQ256

b'0001 1001

EPCQ512/A

b'0010 0000

The 8-bit device identification of the EPCQ device is shifted out on the DATA1 pin on

the falling edge of the DCLK signal.

Figure 14.

Read Device Identification Operation Timing Diagram

nCS

DCLK

DATA0

DATA1

20 21 23 24 25 26 27 28 29 30 31 32

Operation Code (9Fh)

Two Dummy Bytes

15 14 13

MSB

High Impedance

Device ID

Don’t Care

1.7.9. Write Bytes Operation (02h)

This operation allows bytes to be written to the memory. You must execute the write

enable operation before the write bytes operation. After the write bytes operation is

completed, the write enable latch bit in the status register is set to 0.

When you execute the write bytes operation, you shift in the write bytes operation

code, followed by a 3-byte addressing mode (A[23..0]) or a 4-byte addressing mode

(A[31..0]), and at least one data byte on the DATA0 pin. If the eight LSBs

(A[7..0]) are not all 0, all sent data that goes beyond the end of the current page is

not written into the next page. Instead, this data is written at the start address of the

same page. You must ensure the nCS signal is set low during the entire write bytes

operation.

Figure 15.

Write Bytes Operation Timing Diagram

To access the entire EPCQ256 or EPCQ512/A memory, use 4-byte addressing mode. In the 4-byte addressing

mode, the address width is 32-bit address.

DATA0

Operation Code (02h)

24-Bit Address

Data Byte 1

Data Byte 2

Data Byte 256

28 29 30 31 32

nCS

DCLK

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

23 22 21

2072 2073 2074 2075 2076 2077 2078 2079

MSB

If more than 256 data bytes are shifted into the EPCQ device with a write bytes

operation, the previously latched data is discarded and the last 256 bytes are written

to the page. However, if less than 256 data bytes are shifted into the EPCQ device,

they are guaranteed to be written at the specified addresses and the other bytes of

the same page are not affected.

1. Quad-Serial Configuration (EPCQ) Devices Datasheet

CF52012 | 2018.06.01

Quad-Serial Configuration (EPCQ) Devices Datasheet

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