NUC505-YO2N datasheet(9/130 Pages) NUVOTON

9 / 130 page

NUC505

July. 26, 2018

Page 9 of 130

Rev.1.08

FEATURES

NUC505 Features

2.1

Core

─

ARM

® Cortex® -M4F core running up to 100 MHz

─

Supports DSP extension with hardware divider

─

Supports IEEE 754 compliant Floating Point Unit (FPU)

─

Supports Memory Protection Unit (MPU)

─

One 24-bit system timer

─

Supports Power-down mode by WFI and WFE instructions

─

Single-cycle 32-bit hardware multiplier

─

Supports programmable 16 level priorities of Nested Vectored Interrupt Controller

(NVIC)

─

Supports programmable mask-able interrupts

─

Boots from SPI Flash Memory or USB Device

SRAM Memory

─

128 KB embedded SRAM with zero-wait state

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Supports byte-, half-word- and word-access

SPI Memory Interface Controller

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Supports external SPI Flash memory

─

Supports code protection

─

Supports DMA mode for code transfer from SPI Flash memory to SRAM

─

Supports CPU direct read from SPI Flash memory.

─

Supports standard (1-bit), dual (2-bit), and quad (4-bit) I/O transfer mode

─

Supports general SPI master interface protocol

Embedded SPI Flash

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512 KB/ 2 MB SPI Flash

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Configurable program code/data allocation

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Supports 2-wired ICP update through SWD/ICE interface

─

Supports ISP update

─

Supports standard (1-bit), dual (2-bit), and quad (4-bit) I/O transfer mode

─

Supports 100 MHz clock for standard I/O transfer mode

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Supports 80 MHz clock for dual and quad I/O transfer mode

Security for code protection

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128-bit key for code protection against pirating

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Up to 15 times programming of the key

Clock Control

─

Built-in 32.768 kHz internal low speed RC oscillator (LIRC) for RTC function,

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