NUC505-YO2T datasheet(76/130 Pages) NUVOTON

76 / 130 page

NUC505

July. 26, 2018

Page 76 of 130

Rev.1.08

6.2.6

SRAM Memory Organization

The NUC505 supports embedded SRAM with a total of 128 Kbytes and the SRAM organization is

separated to four banks: SRAM bank0, SRAM bank1, SRAM bank2, and SRAM bank3. Each of these

four banks has 32 Kbytes address space and can be accessed simultaneously.



Supports a total of 128 Kbytes SRAM



Supports byte / half word / word write



Supports fixed 32 Kbytes SRAM banks for independent access



Supports remap address to 0x1FF0_0000



Supports remap arbitrary memory block of 128 Kbytes SRAM to 0x0000_0000 by using

vector map module

AHB interface

controller

SRAM decoder

SRAM bank0

SRAM bank1

SRAM decoder

AHB interface

controller

AHB interface

controller

SRAM decoder

SRAM bank2

AHB interface

controller

SRAM decoder

SRAM bank3

Figure 6.2-2 SRAM Block Diagram

Figure 6.2-3 shows the SRAM organization of NUC505. There are four SRAM banks in NUC505 and

each bank is addressed to 32 Kbytes. The bank0 address space is from 0x2000_0000 to

0x2000_7FFF. The bank1 address space is from 0x2000_8000 to 0x2000_FFFF. The bank2 address

space is from 0x2001_0000 to 0x2001_7FFF. The bank3 address space is from 0x2001_8000 to

0x2001_FFFF.

The address of each bank is remapping from 0x2000_0000 to 0x1FF0_0000. CPU can access SRAM

bank0 through 0x2000_0000 to 0x2000_7FFF or 0x1FF0_0000 to 0x1FF0_7FFF, SRAM bank1

through 0x2000_8000 to 0x2000_FFFF or 0x1FF0_8000 to 0x1FF0_FFFF, SRAM bank2 through

0x2001_0000 to 0x2001_7FFF or 0x1FF1_0000 to 0x1FF1_7FFF, and SRAM bank3 through

0x2001_8000 to 0x2001_FFFF or 0x1FF1_8000 to 0x1FF1_FFFF.

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