NUC505-YO2T datasheet(12/130 Pages) NUVOTON

12 / 130 page

NUC505

July. 26, 2018

Page 12 of 130

Rev.1.08

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Supports 1-bit Transfer mode

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Configurable bit length of a transfer word from 8 to 32-bit

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Provides separate 8-level depth transmit and receive FIFO buffers

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Supports MSB first or LSB first transfer sequence

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Supports the byte reorder function

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Supports Byte or Word Suspend mode

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Supports 3-wired, no slave select signal, bi-direction interface

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Supports up to 50 MHz

I

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Supports up to two sets of I

2C devices

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Supports Master/Slave mode

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Bidirectional data transfer between masters and slaves

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Multi-master bus (no central master)

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Arbitration between simultaneously transmitting masters without corruption of

serial data on the bus

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Serial clock synchronization allows devices with different bit rates to communicate

via one serial bus

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Serial clock synchronization can be used as a handshake mechanism to suspend

and resume serial transfer

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Programmable clocks allow versatile rate control

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Supports multiple address recognition (four slave address with mask option)

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Supports SMBus and PMBus

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Supports speed up to 1Mbps

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Supports multi-address Power-down wake-up function

PWM

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Four 16-bit timers

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Programmable duty control of output waveform (PWM)

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Auto reload mode or one-shot pulse mode

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Capture and compare function

RTC

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Supports external power pin RTC_VDD33

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Supports 32.768 kHz crystal oscillation circuit

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Supports RTC counter (second, minute, hour) and calendar counter (day, month,

year)

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Supports Alarm registers (second, minute, hour, day, month, year)

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Supports 32 bytes spare registers

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Wake up from Deep Power-down mode or from Power-down mode

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Supports wake up from Power-down mode by input pin

NUC505-YO2T 数据表(PDF) 12 Page - Nuvoton Technology Corporation

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