MPC7445 datasheet(45/64 Pages) FREESCALE

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MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1

Freescale Semiconductor

System Design Information

8.6 Substrate Capacitors for the MPC7455, 483 CBGA

Figure 23 shows the connectivity of the substrate capacitor pads for the MPC7455, 483 CBGA. All capacitors are

100 nF.

Figure 23. Substrate Bypass Capacitors for the MPC7455, 483 CBGA

System Design Information

This section provides system and thermal design recommendations for successful application of the MPC7455.

9.1 PLL Configuration

The MPC7455 PLL is configured by the PLL_CFG[0:4] signals. For a given SYSCLK (bus) frequency, the PLL

configuration signals set the internal CPU and VCO frequency of operation. The PLL configuration for the

MPC7455 is shown in Table 17 for a set of example frequencies. In this example, shaded cells represent settings

that, for a given SYSCLK frequency, result in core and/or VCO frequencies that do not comply with the 1-GHz

column in Table 8. Note that these configurations were different in devices prior to Rev F; see Section 11.2, “Part

Numbers Not Fully Addressed by This Document,” for more information regarding documentation of prior

revisions.

Capacitor

Pad Number

-1

-2

OVDD

GND

VDD

GND

OVDD

GND

OVDD

GND

VDD

GND

OVDD

GND

AVDD

GND

OVDD

GND

GVDD

GND

C10

GVDD

GND

C11

VDD

GND

C12

GVDD

GND

C3-1

C3-2

C2-2

C1-2

C1-1

C2-1

A1 Corner

C7-2

C7-1

C8-1

C9-1

C9-2

C8-2

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