MPC7445 datasheet(16/64 Pages) FREESCALE

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MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1

Freescale Semiconductor

Electrical and Thermal Characteristics

Figure 3 provides the SYSCLK input timing diagram.

Figure 3. SYSCLK Input Timing Diagram

SYSCLK jitter

—

± 150

—

± 150

—

± 150

—

± 150

4, 6

Internal PLL relock time

—100

µs5

Notes:

1. Caution: The SYSCLK frequency and PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK

(bus) frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or

minimum operating frequencies. Refer to the PLL_CFG[0:4] signal description in Section 9.1, “PLL Configuration,”

for valid PLL_CFG[0:4] settings.

2. Rise and fall times for the SYSCLK input measured from 0.4 to 1.4 V.

3. Timing is guaranteed by design and characterization.

4. This represents total input jitter—short term and long term combined—and is guaranteed by design.

5. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time

required for PLL lock after a stable VDD and SYSCLK are reached during the power-on reset sequence. This

specification also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also

note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the

power-on reset sequence.

6. The SYSCLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low

to allow cascade connected PLL-based devices to track SYSCLK drivers with the specified jitter.

Table 8. Clock AC Timing Specifications (continued)

At recommended operating conditions. See Table 4.

Characteristic

Symbol

Maximum Processor Core Frequency

Unit

Notes

733 MHz

867 MHz

933 MHz

1 GHz

Min

Max

Min

Max

Min

Max

Min

Max

SYSCLK

CVIH

CVIL

VM = Midpoint Voltage (OVDD/2)

tSYSCLK

tKR

tKF

tKHKL

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