MPC859TZP100 datasheet(62/92 Pages) FREESCALE

部件名	MPC859TZP100

功能描述	Hardware Specifications

PDF	92 Pages

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制造商	FREESCALE [Freescale Semiconductor, Inc]

网页	http://www.freescale.com

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MPC866/859 Hardware Speciﬁcations

MOTOROLA

CPM Electrical Characteristics

Figure 61. Ethernet Collision Timing Diagram

Figure 62. Ethernet Receive Timing Diagram

135

RSTRT active delay (from TCLK1 falling edge)

136

RSTRT inactive delay (from TCLK1 falling edge)

137

REJECT width low

—

CLK

138

CLKO1 low to SDACK asserted 2

—20

139

CLKO1 low to SDACK negated 2

—20

1 The ratios SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 2/1.

2 SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.

Table 24. Ethernet Timing (continued)

Num

Characteristic

All Frequencies

Unit

Min

Max

CLSN(CTS1)

120

(Input)

RCLK1

121

RxD1

(Input)

121

RENA(CD1)

(Input)

125

124

123

127

126

Last Bit

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