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MPC859TZP100 数据表(PDF) 16 Page - Freescale Semiconductor, Inc |
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MPC859TZP100 数据表(HTML) 16 Page - Freescale Semiconductor, Inc |
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16 / 92 page  16 MPC866/859 Hardware Specifications MOTOROLA Bus Signal Timing Bus Signal Timing Table 9 shows the timings for the MPC866/859 at 33, 40, 50, and 66 MHz bus operation. The timing for the MPC866/859 bus shown in this table assumes a 50-pF load for maximum delays and a 0-pF load for minimum delays. CLKOUT assumes a 100-pF load maximum delay. Table 7. Frequency Ranges for Standard Part Frequencies (1:1 Bus Mode) Part Freq 50 MHz 66 MHz Min Max Min Max Core 40 50 40 66.67 Bus 40 50 40 66.67 Table 8. Frequency Ranges for Standard Part Frequencies (2:1 Bus Mode) Part Freq 50 MHz 66 MHz 100 MHz 133 MHz Min Max Min Max Min Max Min Max Core 40 50 40 66.67 40 100 40 133.34 Bus 20 25 20 33.33 20 50 20 66.67 Table 9. Bus Operation Timings Num Characteristic 33 MHz 40 MHz 50 MHz 66 MHz Unit Min Max Min Max Min Max Min Max B1 Bus Period (CLKOUT) See Table 7 — — —————— ns B1a EXTCLK to CLKOUT phase skew – 2 +2 – 2 +2 – 2 +2 – 2 +2 ns B1b CLKOUT frequency jitter peak-to-peak — 1 —1—1—1 ns B1c Frequency jitter on EXTCLK — 0.50 — 0.50 — 0.50 — 0.50 % B1d CLKOUT phase jitter peak-to-peak for OSCLK ≥ 15 MHz — 4 —4—4—4 ns CLKOUT phase jitter peak-to-peak for OSCLK < 15 MHz — 5 —5—5—5 ns B2 CLKOUT pulse width low (MIN = 0.4 x B1, MAX = 0.6 x B1) 12.1 18.2 10.0 15.0 8.0 12.0 6.1 9.1 ns B3 CLKOUT pulse width high (MIN = 0.4 x B1, MAX = 0.6 x B1) 12.1 18.2 10.0 15.0 8.0 12.0 6.1 9.1 ns B4 CLKOUT rise time — 4.00 — 4.00 — 4.00 — 4.00 ns B5 CLKOUT fall time — 4.00 — 4.00 — 4.00 — 4.00 ns B7 CLKOUT to A(0:31), BADDR(28:30), RD/WR, BURST, D(0:31), DP(0:3) output hold (MIN = 0.25 x B1) 7.60 — 6.30 — 5.00 — 3.80 — ns Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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