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MPC859TZP100 数据表(PDF) 63 Page - Freescale Semiconductor, Inc

部件名 MPC859TZP100
功能描述  Hardware Specifications
PDF  92 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

MPC859TZP100 数据表(HTML) 63 Page - Freescale Semiconductor, Inc

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MOTOROLA
MPC866/859 Hardware Specifications
63
CPM Electrical Characteristics
Figure 63. Ethernet Transmit Timing Diagram
Figure 64. CAM Interface Receive Start Timing Diagram
Figure 65. CAM Interface REJECT Timing Diagram
TCLK1
128
TxD1
(Output)
128
TENA(RTS1)
(Input)
Notes:
Transmit clock invert (TCI) bit in GSMR is set.
If RENA is deasserted before TENA, or RENA is not asserted at all during transmit, then the
CSL bit is set in the buffer descriptor at the end of the frame transmission.
1.
2.
RENA(CD1)
(Input)
133
134
132
131
121
129
RCLK1
RxD1
(Input)
RSTRT
(Output)
0
136
125
1
1
BIT1
BIT2
Start Frame Delimiter
REJECT
137
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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