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GD25LE32DVJG 数据表(PDF) 54 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25LE32DVJG 数据表(HTML) 54 Page - GigaDevice Semiconductor (Beijing) Inc. |
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54 / 72 page ![]() 1.8V Uniform Sector Dual and Quad Serial Flash GD25LE32D 54 8. ELECTRICAL CHARACTERISTICS 8.1 Power-On Timing Figure39. Power-On Timing Sequence Diagram VCC(max.) VCC(min.) tVSL Chip Selection is not allowed Full Device Access Allowed Time VPWD(max.) tPWD VCC Table3. Power-Up Timing and Write Inhibit Threshold Symbol Parameter Min. Max. Unit tVSL VCC (min.) to device operation 1.8 ms VWI Write Inhibit Voltage 1 1.4 V VPWD VCC voltage needed to below VPWD for ensuring initialization will occur 0.5 V tPWD The minimum duration for ensuring initialization will occur 300 μs 8.2 Initial Delivery State The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFH).The Status Register contains 00H (all Status Register bits are 0). 8.3 Absolute Maximum Ratings Parameter Value Unit Ambient Operating Temperature -40 to 85 -40 to 105 -40 to 125 ℃ Storage Temperature -65 to 150 ℃ Applied Input/Output Voltage -0.6 to VCC+0.4 V Transient Input/Output Voltage (note: overshoot) -2.0 to VCC+2.0 V VCC -0.6 to 2.5 V |
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