TC9204M
Preliminary Data Sheet
Pin Listing (continued)
No.
Pin label
Type
Description
101
NC
NA
Reserved for future use
102
NC
NA
Reserved for future use
103
NC
NA
Reserved for future use
104
NC
NA
Reserved for future use
105
Gtxck
I
The 125Mhz reference clock for 1000Mbps operating mode. This clock is
used as a reference clock for the GMII transmission clock for every port.
106
Vdd 2.0
P
Digital +2.0V power supply for core
107
BcstLED
I/Opd The led can signal either filtering of broadcast frames. Also the led
remains lit if the POST test fails, which indicates a faulty chip.
108
OvUnLED
O
The led is lit whenever a unicast packets overflow condition is reached
and some frames are dropped by the buffer management engine.
109
Vss 2.0
G
Digital ground for core
110
Sysck
I
The 25Mhz system clock.
111
Reset
Ipus
General reset. Active Low.
112
Txd27
I/Opd GMII transmit data - most significant bit
113
Txd26
I/Opd GMII transmit data - bit 6
114
Txd25
I/Opd GMII transmit data - bit 5
115
Txd24
O
GMII transmit data - bit 4
Txd23
GMII/MII transmit data - bit 3
116
PriBndw1
I/Opd
Priority bandwidth configuration pins.
PriBndw(1)is latched on reset
117
Vdd 2.0
P
Digital +2.0V power supply for core
Txd22
GMII/MII transmit data - bit 2
118
PriBndw0
I/Opu
Priority bandwidth configuration pins. These configuration pins allow the
bandwidth percentage assigned to a priority packet queue to be modified
to certain hardwired levels. PriBndw chooses between 4 hardwired
spreading percentage schemes among the 4 priority queues of each port.
PriBndw(0)is latched on reset
Txd21
GMII/MII transmit data - bit 1
PriClass[2] is latched on reset
119
priclass21
I/Opd
Priority class - most significant bit.
Txd20
GMII/MII transmit data - least significant bit
120
priclass20
I/Opu
Priority class - least significant bit. Sets priority level per port basis.
PriClass[2] - '00' - port 2 low priority
PriClass[2] - '01' - port 2 has normal priority
PriClass[2] - '10' - port 2 has high priority
PriClass[2] - '11' - port 2 has very high priority
PriClass[2] is latched on reset
121
Txen2
O
GMII/MII transmit enable
122
Gtxclk2
O
GMII transmit clock
123
Vss 2.0
G
Digital ground for core
124
Txer2
I/Opd Transmit Error
125
Txclk2
I
MII transmit clock
126
Crs2
Is
MII carrier sense indication
Confidential.
9/49
July 29, 2003
Copyright © 2003, IC Plus Corp.
TC9204M-DS-R05
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